This review describes recent groundbreaking results in Si, Si/SiGe, and dopant-based quantum dots, and it highlights the remarkable advances in Si-based quantum physics that have occurred in the past few years. This progress has been possible thanks to materials development of Si quantum devices, and the physical understanding of quantum effects in silicon. Recent critical steps include the isolation of single electrons, the observation of spin blockade, and single-shot readout of individual electron spins in both dopants and gated quantum dots in Si. Each of these results has come with physics that was not anticipated from previous work in other material systems. These advances underline the significant progress toward the realization of spin quantum bits in a material with a long spin coherence time, crucial for quantum computation and spintronics.

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Silicon quantum electronics

This paper reviews the present knowledge on tantalum pentoxide (Ta 2 O 5 ) thin films and their applications in the field of microelectronics and integrated microtechnologies. Different methods used to produce tantalum oxide layers are described, emphazing elaboration mechanisms and key parameters for each technique. We also review recent advances in the deposition of Ta 2 O 5 in the particular field of microelectronics where high quality layers are required from the structural and electrical points of view. The physical, structural, optical, chemical and electrical properties of tantalum oxide thin films on semiconductors are then presented and essential film parameters, such as optical index, film density or dielectric permittivity, are discussed. After a reminder of the basic mechanisms that control the bulk electrical conduction in insulating films, we carefully examine the origin of leakage currents in Ta 2 O 5 and present the state-of-the-art concerning the insulating behaviour of tantalum oxide layers. Finally, applications of tantalum oxide thin films are presented in the last part of this paper. We show how Ta 2 O 5 has been employed as an antireflection coating, insulating layer, gate oxide, corrosion resistant material, and sensitive layer in a wide variety of components, circuits and sensors.

Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.

Academic and industry research progress in germanium nanodevices

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power ( e.g. , mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g. , neuromorphic computing, hardware security, etc . In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

A review of emerging non-volatile memory (NVM) technologies and applications

http://ieeexplore.ieee.org/iel5/10061/32274/01505457.pdf

The decananometer CMOS era - Is there CMOS after CMOS?

The morphological characterization of local oxidation of silicon (LOCOS) isolation has been carried out by using steam oxidation in the temperature range 1050 to 1180°C and as-grown field oxide thickness between 150 and 600 nm. A bird's beak minimum is observed between 1100 and 1140°C, corresponding to a change in the bird's beak growth mechanism from a diffusion type to a regime dependent on silicon surface oxidation and nitride oxidation rates. For the first time on LOCOS isolation, the improvement of field oxide thinning by reducing field oxide thickness is reported : that enables a possible scaling for subquarter micrometer design rules.

High Temperature Local Oxidation of Silicon Field Isolation Morphological Characterization

FDSOI Technology: A Power Efficient Solution Down to 10nm

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Double Gate Coupling and Quantum Tunneling in Ultrathin SOI MOSFETs

We propose a conceptual modification of the SOI structure, by replacing the buried oxide with an alternative dielectric. Such generalized-SOI structures open new fields of application and improve the performance of CMOS devices. We concentrate on the critical problem of self-heating in advanced SOI MOSFETs (L g = 10-100 nm). An equivalent thermal circuit and 2-D simulations show that self-heating can be dramatically reduced by using buried alumina. Preliminary results related to the fabrication of alumina-bamd SOI are presented.

Simon Deleonibus

Papers

The decananometer CMOS era - Is there CMOS after CMOS?

High Temperature Local Oxidation of Silicon Field Isolation Morphological Characterization

FDSOI Technology: A Power Efficient Solution Down to 10nm

Double Gate Coupling and Quantum Tunneling in Ultrathin SOI MOSFETs

Replacing the box with buried alumina: Improved thermal dissipation in SOI MOSFETs