S
Simon Deleonibus
Researcher at European Automobile Manufacturers Association
Publications - 129
Citations - 1772
Simon Deleonibus is an academic researcher from European Automobile Manufacturers Association. The author has contributed to research in topics: MOSFET & Silicon on insulator. The author has an hindex of 25, co-authored 129 publications receiving 1742 citations. Previous affiliations of Simon Deleonibus include French Alternative Energies and Atomic Energy Commission.
Papers
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Journal ArticleDOI
Experimental Investigation on the Quasi-Ballistic Transport: Part I—Determination of a New Backscattering Coefficient Extraction Methodology
TL;DR: In this article, a new fully experimental method to determine the backscattering coefficient and the ballistic ratio of n-and p-FDSOI and multigate nanodevices is proposed.
Journal ArticleDOI
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate
K. Romanjek,Louis Hutin,C. Le Royer,A. Pouydebasque,Marie-Anne Jaud,Claude Tabone,E. Augendre,Loic Sanchez,J.M. Hartmann,H. Grampeix,V. Mazzocchi,S. Soliveres,R. Truche,Laurent Clavelier,P. Scheiblin,X. Garros,G. Reimbold,Maud Vinet,Fabien Boulanger,Simon Deleonibus +19 more
TL;DR: In this paper, the authors demonstrate for the first time 70nm gate length gate length TiN/HfO 2 pMOSFETs on 200mm GeOI wafers, with excellent performance: I ON Â= 260μA/μm and I OFF Â = 500 Ã 1.0 Â V (without germanide).
Journal ArticleDOI
Advanced SOI MOSFETs with buried alumina and ground plane: self-heating and short-channel effects
TL;DR: In this paper, the authors demonstrate that the thermal dissipation and self-heating in SOI MOSFETs can dramatically be improved by modifying the generic SOI structure: replacement of the buried oxide with buried alumina.
Journal ArticleDOI
Degradation of floating-gate memory reliability by few electron phenomena
G. Molas,Damien Deleruyelle,B. De Salvo,Gerard Ghibaudo,M. GelyGely,L. Perniola,D. Lafond,Simon Deleonibus +7 more
TL;DR: In this paper, a model that quantitatively predicts the intrinsic dispersions of the memory retention time and programming window is proposed and experimental results obtained on ultrascaled memory devices (with an active area as small as 30 nm times 30 nm) with either a continuous poly-Si floating-gate (FG) or silicon nanocrystals are used to validate this model.
Proceedings ArticleDOI
Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS
Olivier Weber,Y. Bogumilowicz,Thomas Ernst,J.M. Hartmann,F. Ducroquet,Francois Andrieu,Cecilia Dupre,Laurent Clavelier,C. Le Royer,Nikolay Cherkashin,Martin Hÿtch,D. Rouchon,H. Dansas,A.M. Papon,V. Carron,Claude Tabone,Simon Deleonibus +16 more
TL;DR: In this paper, the same process for a dual channel integration scheme was used to achieve symmetric n-and p-MOSFET IDsat performance with high-k gate dielectric.