Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications.

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III–V compound semiconductor transistors—from planar to nanowire structures

Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

Low-dimensional semiconductor materials structures, where nanowires are needle-like one-dimensional examples, have developed into one of the most intensely studied fields of science and technology. The subarea described in this review is compound semiconductor nanowires, with the materials covered limited to III-V materials (like GaAs, InAs, GaP, InP,...) and III-nitride materials (GaN, InGaN, AlGaN,...). We review the way in which several innovative synthesis methods constitute the basis for the realization of highly controlled nanowires, and we combine this perspective with one of how the different families of nanowires can contribute to applications. One reason for the very intense research in this field is motivated by what they can offer to main-stream semiconductors, by which ultrahigh performing electronic (e.g., transistors) and photonic (e.g., photovoltaics, photodetectors or LEDs) technologies can be merged with silicon and CMOS. Other important aspects, also covered in the review, deals with synthesis methods that can lead to dramatic reduction of cost of fabrication and opportunities for up-scaling to mass production methods.

Synthesis and Applications of III-V Nanowires

Band-to-band tunneling field-effect transistors (TFETs) have emerged as promising candidates for low-power integration circuits beyond conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and have been demonstrated to overcome the thermionic limit, which results intrinsically in sub-threshold swings of at least 60 mV/dec at room temperature. Here, we demonstrate complementary TFETs based on few-layer black phosphorus, in which multiple top gates create electrostatic doping in the source and drain regions. By electrically tuning the doping types and levels in the source and drain regions, the device can be reconfigured to allow for TFET or MOSFET operation and can be tuned to be n-type or p-type. Owing to the proper choice of materials and careful engineering of device structures, record-high current densities have been achieved in 2D TFETs. Full-band atomistic quantum transport simulations of the fabricated devices agree quantitatively with the current–voltage measurements, which give...

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Complementary Black Phosphorus Tunneling Field-Effect Transistors.

We present a vertical nanowire InAs/GaAsSb/GaSb TFET with a highly scaled InAs diameter (20 nm). The device exhibits a minimum subthreshold swing of 48 mV/dec. for V ds = 0.1–0.5 V and achieves an I on = 10.6 μA/μm for I off = 1 nA/μm at V ds = 0.3 V. The lowest subthreshold swing achieved is 44 mV/dec. at V ds = 0.05 V. Furthermore, a benchmarking is performed against state-of-the-art TFETs and MOSFETs demonstrating a record high I60 and performance benefits for V ds between 0.1 and 0.3 V.

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Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and I on = 10 μA/μm for I off = 1 nA/μm at V ds = 0.3 V

We demonstrate a vertical InAs nanowire MOSFET integrated on Si substrate with an extrinsic peak cut-off frequency of 103 GHz and a maximum oscillation frequency of 155 GHz. The transistor has a transconductance of 730 mS/mm and is based on arrays of nanowires with gate-all-around and high-κ gate dielectric. Furthermore, small-signal modeling shows a ~80% reduction of the total parasitic gate capacitance when the metal pad overlap in the transistors is reduced through additional patterning.

High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InxGa1–xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essent...

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Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade

We demonstrate improved performance due to enhanced electrostatic control achieved by diameter scaling and gate placement in vertical InAs-GaSb tunneling field-effect transistors integrated on Si substrates. The best subthreshold swing, 68 mV/decade at $V_{\textrm {DS}}= 0.3$ V, was achieved for a device with 20-nm InAs diameter. The on-current for the same device was 35 $\mu \text{A}/\mu \text{m}$ at $V_{\textrm {GS}}=0.5$ V and $V_{\textrm {DS}}= 0.5$ V. The fabrication technique used allow downscaling of the InAs diameter down to 11 nm with a flexible gate placement.

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Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.

Elvedin Memisevic

Papers

Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and I on = 10 μA/μm for I off = 1 nA/μm at V ds = 0.3 V

High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade

Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.