The kinetics and chemistry of Si‐SiO2 interface trap annealing are examined in detail Measurements of interface trap density Dit as a function of anneal time were performed with several process variables as parameters: oxide thickness, anneal ambient, temperature, bulk carrier type, metallization damage, and orientation Experiments were carried out using rapid thermal processing and capacitance‐voltage measurements of aluminum gate metal‐oxide‐semiconductor capacitors Anneal temperature and crystal orientation have the strongest effect on the kinetics 〈100〉 interfaces can be described by a power‐law temporal variation; 〈111〉 kinetics are slightly more complicated In both cases the experimentally observed anneal behavior is in conflict with the commonly used second‐order surface recombination model We propose a two‐reaction model involving atomic hydrogen dimerization and hydrogen/interface trap reactions This model sucessfully predicts anneal kinetics over a temperature range of 170–500 °C, representing a 106 dynamic range in anneal rates The difference in anneal behavior between 〈111〉 and 〈100〉 interfaces is explained by postulating different trap anneal mechanisms for the Pb0 and Pb1 defect centers This hypothesis is supported by trap production kinetics induced by extended anneals

Chemistry of Si‐SiO2 interface trap annealing

Two methods have been developed for analyzing MOS transients. One method is analytical and uses the quasi-static approximation. It is useful when the stray capacitance dominates MOS transient performance. The second method is numericaf and uses a new boundary value method which can be applied over a wide range of operating speeds. This method includes secondary effects and nonuniform doping. The validity and Iimits for both methods are verified by comparison with measurements. Transit-time delay and charge-pumping effects are also analyzed using the numerical method. Examples of short-channel behavior of MOS devices are included.

Transient Analysis of MOS Transistors

In this paper, we describe a complete MOSFET model developed for circuit simulation based on fully consistent physical concept. The model describes all transistor characteristics as a function of surface potentials, which are calculated iteratively at each applied voltage under the charge-sheet approximation. The key idea of this development is to put as much physics as possible into the equations describing the surface potentials. Since the model includes both the drift and the diffusion contributions, a single equation is valid from the subthreshold to the saturation regions. Contrary to the expectation, the results show that our semi-implicit model including the iteration procedures can even reduce the CPU time significantly in comparison with a conventional model similar to BSIM2 including short-channel effects. This is due to the consistent description of the model equations for all transistor characteristics, which results in more straightforward device equations, once the surface potentials have been computed.

Unified complete MOSFET model for analysis of digital and analog circuits

Two methods have been developed for analyzing MOS transients. One method is analytical and uses the quasi-static approximation. It is useful when the stray capacitance dominates MOS transient performance. The second method is numerical and uses a new boundary value method which can be applied over a wide range of operating speeds. This method includes secondary effects and nonuniform doping, The validity and limits for both methods are verified by comparison with measurements. Transit-time delay and charge-pumping effects are also analyzed using the numerical method. Examples of short-channel behavior of MOS devices are included.

Transient analysis of MOS transistors

A new non-quasi-static (NQS) MOSFET model, which is applicable for both large-signal transient and small-signal ac analysis, has been developed. It employs a physical relaxation time approach to take care of the finite channel charging time to reach equilibrium and the effect of instantaneous channel charge re-distribution. The NQS model is formulated independently from the dc I-V and the charge-capacitor model, thus can be easily applied to any existing simulators. The model has been implemented in the newly released BSIM3 version 3, and comparison has been made among this model, common quasi-static (QS) SPICE models and PISCES two-dimensional (2-D) numerical device simulator. While predicting accurate NQS behavior, the time penalty for using the new model is only about 20-30% more than the common QS models. It is much less than the time required by other NQS models reported. Limitations and compromises between simplicity, efficiency and accuracy are also discussed.

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A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation

Two-dimensional oxidation is a moving-boundary problem involving steady-state oxidant diffusion and incompressible viscous flow. To solve the kinetic equations for the two-dimensional oxidation model, this work introduces a general numerical method that combines pressure/ velocity iteration with a boundary-value technique.

A general solution method for two-dimensional nonplanar oxidation

A method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs, comprising the steps of: computing a statistically worst case interconnect delay from randomly generated material and geometry values characterizing an integrated circuit interconnect process; computing a representative set of material and geometry values corresponding to the statistically worst case interconnect delay; and computing R,C parameters corresponding to the statistically worst case interconnect delay from the representative set of material and geometry values.

Method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs

As scaling is continued down to deep submicron, interconnects become dominating the performance, signal integrity, and reliability of IC chips. However, due to the short history, not much work has been done on the overall interconnect modeling, especially interconnect characterization and statistical interconnect modeling. In interconnect characterization, more systematic methodology should be established in interconnect test structure design and their characterization. New test structures and characterization methods should be developed to characterize the advanced interconnect technology such as low K dielectric and copper. 2D interconnect model library generation has been done by the 2D finite-difference method or finite-element method. However, it takes too long to generate 3D interconnect model library due to the increase of 3D basic structures. Fast multi-pole method or measured equation of inversion are used to speed up the 3D library generation. To avoid errors due to 3D structure partitioning 3D Monte Carlo method is used to simulate the global nets. The ever-increasing clock frequency makes inductive effects more significant. However, it is very challenging to model the on-chip inductance due to its long-range interaction and wide return paths. Worst-case interconnect modeling has been done by the skew-corner method or root-sum-square method. Both methods are too conservative. The newly developed SWIM (Statistically-based Worst-case Interconnect Model generator) improves the worst-case delay within 20%.

Soo-Young Oh

Papers

Transient Analysis of MOS Transistors

Transient analysis of MOS transistors

A general solution method for two-dimensional nonplanar oxidation

Method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs

Interconnect modeling for VLSIs