Srinivasan Gopal

TL;DR: Few works at low-GHz frequencies are reported to improve the PA's intrinsic linearity using a varactor-or PMOS-based AM-PM correction methods, however, the inclusion of additional capacitive element to correct AM- PM degrades gain and efficiency, which is not optimal for mmW frequencies.

TL;DR: A parasitic-aware tuned-load with a high-order harmonic-resonance network is proposed to shape the current and voltage waveforms for the CCF PA, reducing detrimental loading effect on harmonic-tuned load while enhancing power efficiency and stability.

TL;DR: This proposed inductive linearization method mitigates the large gain reduction problem in traditional capacitor-based linearization approaches while consuming no extra dc power or without introducing additional control circuitry.

TL;DR: The proposed CSVG-LNA alleviates high power consumption and large noise-figure (NF) variation problems in traditional approaches and achieves 1.5X improvement in FoM in comparison to state-of-the-arts mm-wave variable-gain CMOS LNAs.

TL;DR: Large-scale parallel implementation of matrix multiply and accumulate (MAC) core poses significant energy and area constraints in analog voltage domain under reduced supply voltage, so a spatial multi-bit sub-1-V time-domain matrix multiplier interface is presented using multi- bit back-gate-driven delay elements as a scalable alternative for various approximate computing applications.