S
Subin Lee
Researcher at Korea Institute of Science and Technology
Publications - 16
Citations - 209
Subin Lee is an academic researcher from Korea Institute of Science and Technology. The author has contributed to research in topics: Medicine & Electrode. The author has an hindex of 7, co-authored 11 publications receiving 154 citations. Previous affiliations of Subin Lee include University of Wisconsin-Madison.
Papers
More filters
Journal ArticleDOI
A Compact Parylene-Coated WLAN Flexible Antenna for Implantable Electronics
Yei Hwan Jung,Yijie Qiu,Subin Lee,Ting-Yen Shih,Yuehang Xu,Ruimin Xu,Juhwan Lee,Amelia A. Schendel,Weigan Lin,Justin C. Williams,Nader Behdad,Zhenqiang Ma +11 more
TL;DR: In this article, a planar flexible antenna for wireless local area network (WLAN) using simple microfabrication techniques that are compatible with existing state-of-the-art flexible electronic devices is presented.
Journal ArticleDOI
Stretchable Twisted‐Pair Transmission Lines for Microwave Frequency Wearable Electronics
Yei Hwan Jung,Juhwan Lee,Yijie Qiu,Namki Cho,Sang June Cho,Huilong Zhang,Subin Lee,Tong June Kim,Shaoqin Gong,Zhenqiang Ma +9 more
TL;DR: In this paper, a twisted-pair design integrated into thin-film serpentine microstructure was proposed to minimize electromagnetic interference, such that the line's performance is minimally affected by the environment in close proximity, allowing its use in thinfilm bioelectronics, such as the epidermal electronic system.
Journal ArticleDOI
Compact parylene-c-coated flexible antenna for WLAN and upper-band UWB applications
Yijie Qiu,Yei Hwan Jung,Subin Lee,Ting-Yen Shih,Juhwan Lee,Yuehang Xu,Ruimin Xu,Weigan Lin,Nader Behdad,Zhenqiang Ma +9 more
TL;DR: In this article, a bio-compatible ultra-thin parylene-c is fabricated on a thin polyimide substrate with a thickness of 127 μm, which is suitable for integration with flexible electronic devices.
Journal ArticleDOI
Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III–V and Ge Materials
Sanghyeon Kim,Seongkwang Kim,Jae-Phil Shim,Dae-Myeong Geum,Gun Wu Ju,Hansung Kim,Heejeong Lim,Hyeong-Rak Lim,Jae-Hoon Han,Subin Lee,Hosung Kim,Pavlo Bidenko,Chang-Mo Kang,Dong-Seon Lee,Jin Dong Song,Won Jun Choi,Hyung-jun Kim +16 more
TL;DR: In this article, a low temperature III-V and Ge layer stacking process using wafer bonding and epitaxial lift-off was developed to solve the processing temperature limit for top side devices in order to ensure proper performance of bottom side devices.
Journal ArticleDOI
Simulation Study on the Design of Sub- $kT/q$ Non-Hysteretic Negative Capacitance FET Using Capacitance Matching
TL;DR: In this article, a general approach for matching arbitrary MOSFETs with various ferroelectric (FE) materials was presented for the first time, in which the desired operation conditions were received for specific structures and materials, and with respect to the base structure, certain types of FEs are more preferable to obtain the sub-kT/q operation in a non-hysteretic manner for the wide band of applied voltages.