Pavlo Bidenko

TL;DR: In this article, a low temperature III-V and Ge layer stacking process using wafer bonding and epitaxial lift-off was developed to solve the processing temperature limit for top side devices in order to ensure proper performance of bottom side devices.

TL;DR: In this article, a general approach for matching arbitrary MOSFETs with various ferroelectric (FE) materials was presented for the first time, in which the desired operation conditions were received for specific structures and materials, and with respect to the base structure, certain types of FEs are more preferable to obtain the sub-kT/q operation in a non-hysteretic manner for the wide band of applied voltages.

TL;DR: 3D stackable synaptic transistors for 3D ANNs, which would be the strongest candidate in future computing systems by minimizing power consumption in the interconnection, are suggested and reported.

TL;DR: In this paper, a type-II superlattice (T2SL) barrier that is homogeneous with the T2SL absorber layer was proposed to resolve the drawbacks of the AlGaSb barrier.

TL;DR: In this article, the authors investigated the charge enhancement effect in a SIS capacitor with ferroelectric (FE) materials utilized by the negative capacitance (NC) effect and proposed an NC SIS optical phase modulator to enhance this effect.