Showing papers in "Solid-state Electronics in 2010"

Performance estimation of junctionless multigate transistors

Abstract: This paper describes the simulation of the electrical characteristics of a new transistor concept called the ‘‘Junctionless Multigate Field-Effect Transistor (MuGFET)”. The proposed device has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversion-mode devices with PN junctions at the source and drain. The simulation results indicate that the junctionless MuGFET is a very promising candidate for future decananometer MOSFET applications.

Over 100 A operation normally-off AlGaN/GaN hybrid MOS-HFET on Si substrate with high-breakdown voltage

Abstract: The demonstration of a normally-off n-channel AlGaN/GaN hybrid metal–oxide–semiconductor heterojunction field-effect transistor (MOS-HFET) on Si substrate for large-current operation is reported. The AlGaN/GaN hybrid MOS-HFET has the merits of both a MOS channel and an AlGaN/GaN heterostructure with high mobility two dimensional electron gases (2DEG). The maximum drain current of over 100 A with 2 μm channel length and 340 mm channel width is performed. This is the best value for a normally-off GaN-based field-effect transistor. The specific on-state resistance is 9.3 mΩ cm 2 . The fabricated device also exhibits good normally-off operation with the threshold voltage of 2.7 V and the breakdown voltage of over 600 V.

Hydrogen-induced improvements in electrical characteristics of a-IGZO thin-film transistors

Abstract: This study investigates the effect of hydrogen incorporation on amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs). The threshold voltage ( V th ) and subthreshold swing ( SS ) of hydrogen-incorporated a-IGZO TFTs were improved, and the threshold voltage shift (Δ V th ) in hysteresis loop was also suppressed from 4 V to 2 V. The physical property and chemical composition of a-IGZO films were analyzed by X-ray diffraction and X-ray photoelectron spectroscopy, respectively. Experimental results show that the hydrogen-induced passivation of the interface trap states between active layer and dielectric is responsible for the improvement of SS and V th .

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Abstract: The multi-gate architecture is considered as a key enabler for further CMOS scaling thanks to its improved electrostatics and short-channel effect control. FinFETs represent one of the architectures of interest within that family together with Ω-gates, Π-gates, gate-all-around… They can readily be manufactured starting from SOI or bulk substrates even though more efforts have been dedicated to the SOI option so far. We report in this work an extensive benchmark of their critical electrical figures of merit (FOM) and their limitations. Both alternatives show better scalability (threshold voltage – Vt vs. L) than PLANAR CMOS and exhibit similar intrinsic device performance (Ioff vs. Ion). Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced threshold voltage mismatch. Using an optimized integration to minimize parasitic capacitances and resistances we demonstrate high-performing FinFET ring-oscillators with delays down to 10 ps/stage for both SOI and bulk FinFETs. SRAM cells are also reported to work, scaling similarly with the supply voltage (VDD) for the two FinFET integration schemes.

Limits on vanadium oxide Mott metal–insulator transition field-effect transistors

Abstract: There have been numerous proposals for use of metal–oxide materials as an alternative to semiconductors in field-effect transistors (FET), as current Si FET technology inevitably encounters intrinsic scaling limitations. We report on device-independent power–delay characteristics of potential VO2-based field induced Mott transistors and compare scaling limits to that of Si. Since the critical electric field for metal–insulator transition (MIT) in VO2 is similar to the breakdown field of Si, and due to the inherent possibility of further scaling along one direction in VO2, both materials exhibit similar lower bounds on switching energy. MIT in VO2 results in free carrier concentration several orders of magnitude larger than that of Si, easily overcoming the carrier transit time limits of conventional semiconductor MOSFETs. VO2 switching speed is constrained by the kinetics of the phase transition and more importantly limited thermal dissipation. Our simple model predicts an intrinsic VO2 material lower bound switching time of the order of 0.5 ps at a power transfer of 0.1 μ W .

Experimental measurement of work function in doped silicon surfaces

Abstract: Theory and experimental measurement of work function for electrons in doped silicon surfaces are presented in the article. Definitions of work function and of the local work function are given in the introduction. It was shown, that the value of work function defines the position of Fermi energy level. Numerical calculations of surface potential and electric field for theoretical semiconductor surface models show the difference between finite and infinite surfaces. Photovoltage dependence on charge carriers injection ratio for doped silicon surface was numerically calculated as well. Experimentally determined Fermi energies of doped silicon samples show good agreement with theory for low and moderately doped samples only. Appropriate explanations of disagreement between theory and experiment are given in the conclusion. Suggestions for the system improvement are presented in the Appendix.

Thermal design and analysis of multi-chip LED module with ceramic substrate

Abstract: In this paper, multi-chip LED modules with aluminum nitride (AlN), Al and aluminum oxide (Al2O3) based substrates were successfully designed, fabricated and investigated. Finite element method (FEM) and electrical test method were used to evaluate the thermal performance of LED modules. Both simulation and experimental results show that the module with AlN-based substrate exhibits better thermal performances than the two others. Moreover, AlN-based substrate LED module shows the best optical performances. The optical performances of the LED modules with different substrates not only verify that the optical output and degradation of LED has a direct relation with the input current, but also show that the degradation could begin earlier if the thermal dissipation is not managed well.

Ultra-thin chip technology and applications, a new paradigm in silicon technology

Abstract: Ultra-thin chip technology has potential to provide solutions for overcoming bottlenecks in silicon technology and for leading to new applications. This, however, requires new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. Therefore, ultra-thin chips and the related applications represent a new paradigm in silicon technology. The paper highlights the prominent applications of ultra-thin chips, alerts to the related technological issues and compares the candidate enabling technologies.

Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below

Abstract: In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32 nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299μm2 SRAM cell while maintaining an SNM of 296 mV@Vdd 1.1 V.

Impact of circuit assist methods on margin and performance in 6T SRAM

Abstract: Large scale 6T SRAM beyond 65 nm will increasingly rely on assist methods to overcome the functional limitations associated with scaling and the inherent read stability/write margin trade off. The primary focus of the circuit assist methods has been improved read or write margin with less attention given to the implications for performance. In this work, we introduce margin sensitivity and margin/delay analysis tools for assessing the functional effectiveness of the bias based assist methods and show the direct implications on voltage sensitive yield. A margin/delay analysis of bias based circuit assist methods is presented, highlighting the assist impact on the functional metrics, margin and performance. A means of categorizing the assist methods is developed to provide a first order understanding of the underlying mechanisms. The analysis spans four generations of low power technologies to show the trends and long term effectiveness of the circuit assist techniques in future low power bulk technologies.

Influence of sputtering pressure on morphological, mechanical and electrical properties of Al-doped ZnO films

Abstract: Al-doped ZnO (AZO) films were deposited on glass substrates by pulsed DC sputtering technique with various working pressures in the range of 1–15 mTorr. A relationship between the morphological, mechanical and electrical properties of sputtered AZO films was studied as a function of sputtering pressure. The sputtered films were highly c-axis oriented. The n-type conductivity in AZO films was observed due to the substitutional doping of Al. AZO films deposited at 3 mTorr have shown an electrical resistivity of 2.2 × 10−4 Ω cm and high transmittance in visible range with better mechanical properties. For higher sputtering pressures an increase in the resistivity was observed due to a decrease in the mobility and the carrier concentration. The lower sputtering pressure was found suitable for the fabrication of low-cost transparent conductive oxide layer for futuristic electronic devices.

Highly durable and flexible memory based on resistance switching

Abstract: Resistance random access memory (RRAM) consisting of stacked Al/TiO x /Al structure is demonstrated on a flexible and transparent substrate. To improve cell to cell uniformity, TiO x formed by atomic layer deposition is used for resistive switching material. The simple cross-bar structure of the RRAM and good ductility of aluminum electrode results in excellent flexibility and mechanical endurance. Particularly, bipolar and unipolar resistive switching (BRS, URS) behavior appeared simultaneously were investigated. Depending on the current compliance, BRS or URS could be selectively observed. Furthermore, the permanent transition from BRS to URS was observed with a specific current compliance. To understand this transition behavior, the γ-ray irradiation effect into resistive switching is primarily investigated.

Diamond MOSFET: An innovative layout to improve performance of ICs

Abstract: A new planar MOSFET structure is proposed through a simple layout change, which modifies the gate geometric shape from rectangular to hexagonal in order to use the “corner effect concept” to enhance the resultant longitudinal (parallel) electric field, drift velocity of mobile carriers in the channel, drain current, transconductance, Early voltage and on-resistance in comparison to the equivalent conventional parameters. This paper is conceptual and performs a comparative analyzes between conventional and Diamond Partially-Depleted SOI nMOSFETs by 3D numerical simulations to understand the advantages and disadvantages of this innovative device compared to the conventional counterpart, keeping the same gate area, geometric factor and bias conditions. A simple analytical model for the drain current was proposed and tested for the Diamond transistor. Since we found better results of the Diamond SOI nMOSFETs we believe that, this innovative layout can be a new alternative for analog and digital integrated circuit applications for whatever area it may be needed, without any extra burden to the current technology. This layout approach can also be applied for any planar or 3D transistors technologies.

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

Abstract: This paper aims at presenting a detailed and comprehensive study of the influence of space-charge condition at the substrate/BOX interface. as a function of the gate length and substrate bias. oil both the front threshold voltage (V-thr,) and subthreshold slope (S), for sub-32 nm Ultra-Thin Body (UTB) SOI MOSFETs with two different BOX thicknesses: either standard 145 mn (UTB) or thin 11.5 nm (UTB2). This Study details for the first time, the important impact of the substrate/BOX interface regime variations with gate length from 1 mu m clown to 25 nm, substrate bias and BOX thickness together, on the mean channel position into film and its related impact oil the electrical parameters V-thr and S Experimental results and conclusions are also completed and enlightened by ATLAS simulations and analytical modeling. (C) 2009 Elsevier Ltd. All rights reserved

An analytical model for current–voltage characteristics of AlGaN/GaN HEMTs in presence of self-heating effect

Abstract: A 2-D analytical thermal model for the I–V characteristics of AlGaN/GaN is presented. The effect of self-heating is studied by investigating the temperature effects on various parameters: the 2DEG sheet carrier density, the Fermi level, the electron mobility, the saturation velocity and the critical field. After incorporating self-heating effect in calculations of current–voltage characteristics, our results agreed well with published experimental data.

Function by defects at the atomic scale – New concepts for non-volatile memories

Abstract: A survey of non-volatile, highly scalable memory devices which utilize dedicated resistive switching phenomena in nanoscale chalcogenide-based memory cells is presented. We introduce the basic operation principle of the phase change mechanism, the thermochemical mechanism, and the valence change mechanism and we discuss the crucial role of structural defects in the switching processes. We show how this role is determined by the atomic structure of the defects, the electronic defect states, and/or the ion transport properties of the defects. The electronic structure of the systems in different resistance states is described in the light of the chemical bonds involved. While for phase-change alloys the interplay of ionicity and hybridization in the crystalline and in the amorphous phase determine the resistances, the local redox reaction at the site of extended defects, the change in the oxygen stoichiometry, and the resulting change in the occupancy of relevant orbitals play the major role in the thermochemical and the valence change mechanism. Phase transformations are not only discussed for phase-change alloys but also for both other types of switching processes. The switching kinetics as well as the ultimate scalability of switching cells is related to structural defects in the materials.

Multi-Subband Monte Carlo study of device orientation effects in ultra-short channel DGSOI

Abstract: State-of-the-Art devices in mass production are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Multi-gate devices based on SOI technology, are one of the best candidates to become a standard solution to overcome the problems arising from such aggressive scaling. Moreover, the flexibility of SOI wafers and processes allows the use of different channel materials and substrate orientations to enhance the performance of CMOS circuits. This paper studies the electron transport in DGSOI devices with aggressive scaling and the role of different confinement and transport directions in the characteristics of next generation devices using a Multi-Subband Ensemble Monte Carlo simulator (MSB-EMC). Our simulations show that transport effective mass, and subband redistribution are the main factors that affect drift and scattering processes and, therefore, the general performance of DGSOI devices when orientation is changed.

Interface and electrical properties of La-silicate for direct contact of high-k with silicon

Abstract: Chemical bonding states and electrical characteristics of a La-silicate formed as a compositional transition layer at La2O3/Si interface has been examined. A direct contact of a high-k gate dielectric with Si substrate has been achieved without forming SiO2-based interfacial layer by forming a compositionally graded La-silicate layer, which is advantageous for equivalent oxide thickness (EOT) scaling. A transistor operation with an EOT of 0.48 nm has been demonstrated with low temperature annealing, however a degradation of effective mobility (μeff) has been observed. A high μeff of 300 cm2/V s with relatively low interfacial state density (Dit) of 1011 cm−2/eV can be achieved when annealed at 500 °C, indicating fairly nice interface properties of silicate/Si substrate. Mobility analysis has revealed an additional Coulomb scattering below an EOT of 1.2 nm, which is in good agreement with the negative shifts in threshold and flatband voltages. Moreover, increase in Dit and subthreshold slope have been observed while decreasing the EOT, suggesting the influence of metal atoms diffused from the gate electrode. A mobility degradation model is proposed using metal induced defects generation.

Simple and efficient modeling of the E–k relationship and low-field mobility in Graphene Nano-Ribbons

Abstract: This paper proposes a simple analytical formulation for the dispersion relationship of extended electronic states in Graphene Nano-Ribbons (GNRs). The model has been validated by comparison with Tight-Binding calculation of GNRs in the presence of edge disorder. The model is suited for inclusion in semiclassical models for GNRs featuring widths down to approximately 2 nm. Monte-Carlo simulations accounting for phonons and edge roughness scattering are then used to understand the ribbon width of the low-field mobility. The mechanisms responsible for the low mobility values measured in narrow ribbons compared to graphene sheets are the increased phonon scattering rate and mobility effective mass due to the strong band structure modification induced by the reduced lateral dimensions and the increased scattering with the edges. However, scattering with phonons and with edges is not sufficient to reproduce the experimental mobility on insulating substrates, suggesting that the effect of remote polar phonons originating in the substrate can be significant in graphene based devices.

Estimation of amorphous fraction in multilevel phase-change memory cells

Abstract: The effective thickness of the amorphous chalcogenide part within the active element of a phase-change memory cell is estimated through electrical measurements. Current–voltage characteristics obtained at various intermediate cell states are fitted with the trap-limited subthreshold transport model of [9] and the amorphous part thickness is then extracted. Several cell electrical measures, such as the resistance and the threshold voltage, are shown to closely relate to the estimated parameter. The results serve to further validate the trap-limited conduction model, as well as the series phase distribution hypothesis in the active layer of a phase-change memory cell.

Hall mobility reduction in single-crystalline silicon gradually compensated by thermal donors activation

Abstract: This letter focuses on the variation of the Hall majority carrier mobility with the dopant compensation level in purely Boron-doped Czochralski grown silicon single crystals. Compensation was varied continuously at the sample scale via a step by step activation of the oxygen-based thermal donors. At room temperature, we show a strong drop in mobility for high compensation levels in both p- and n-type Si. Mobility models taking into account carrier scattering on ionized impurities and phonons could not reproduce this drop. We conclude that a specific effect of compensation must be taken into account to explain the observed behaviour. We qualitatively discuss physical mechanisms susceptible to reduce mobility in highly compensated Si.

Enhancement of electrical performance in In2O3 thin-film transistors by improving the densification and surface morphology of channel layers

Abstract: We report on the fabrication of bottom-gate thin-film transistors (TFTs) using indium-oxide (In2O3) thin films as active channel layers. The films were deposited on thermally grown silicon dioxide (SiO2)/n-type silicon (Si) at room temperature (RT) by radio-frequency (RF) magnetron sputtering. The effect of deposition pressure on the performance of In2O3-TFTs was investigated in detail. A significant improvement of the device performance was observed for In2O3-TFTs with the decrease of the working pressure, which is attributed to enhanced densification, better surface morphology of the In2O3 channel layers prepared at lower deposition pressure. The fabricated TFT with optimal device performance exhibited a field-effect mobility (μFE) of 31.6 cm2 V−1 s−1, a drain current on/off ratio of ∼107, a low off drain current of about 10−10 A and a threshold voltage of 7.8 V. Good device performance and low processing temperature make the In2O3-TFTs suitable for the potential applications in the transparent electronics.

Fabrication and characterization of p-Si nanowires/ZnO film heterojunction diode

Abstract: Vertical aligned p-Si nanowires were fabricated by electroless wet chemical etching of Si wafer. p-Si nanowires/ZnO thin film heterojunction diode was fabricated by depositing ZnO thin film on vertically aligned p-Si nanowire arrays. Optical studies revealed that the Si nanowire surface has porous silicon like structure. The junction properties were evaluated by measuring I – V and C – V characteristics. I – V characteristics exhibited well defined rectifying behavior with a turn-on voltage of 2.26 V and ideality factor of 4.5.

Self-aligned inversion-channel In0.75Ga0.25As metal–oxide–semiconductor field-effect-transistors using UHV-Al2O3/Ga2O3(Gd2O3) and ALD-Al2O3 as gate dielectrics

Abstract: High-performance self-aligned inversion-channel In 0.75 Ga 0.25 As n -MOSFETs using in situ ultra-high-vacuum (UHV) deposited Al 2 O 3 /Ga 2 O 3 (Gd 2 O 3 ) [GGO] and ex-situ atomic-layer-deposited (ALD) Al 2 O 3 as gate dielectrics have been fabricated. Both devices exhibit high drain currents and transconductances. A 1.2 μm-gate-length In 0.75 Ga 0.25 As MOSFET using Al 2 O 3 (2 nm-thick)/GGO (13 nm-thick) gate dielectric demonstrated a maximum drain current of 970 μA/μm, a peak transconductance of 410 μS/μm, and a peak mobility of 1560 cm 2 /V s. A maximum drain current of 740 μA/μm and a peak transconductance of 325 μS/μm were exhibited by a 1 μm-gate-length In 0.75 Ga 0.25 As MOSFET using ALD-Al 2 O 3 (6 nm-thick). A comparison between the inversion-channel InGaAs MOSFETs with gate dielectrics using the UHV- and ALD-approaches, and fabricated using the same self-aligned process, was carried out to provide insights for achieving InGaAs MOSFETs with even higher device performances. The comparison in the device performances was extended to cover representative enhancement-mode InGaAs MOSFETs, including self-aligned inversion-channel, non-self-aligned inversion-channel, and flat-band, or buried channel-type of E-mode (non inversion-channel) III–V devices.

Dependence of ohmic contact resistance on barrier thickness of AlN/GaN HEMT structures

Abstract: A multi-faceted study on the reduction of ohmic contact resistance to AlN/GaN-based heterostructures is presented. Minimum contact resistance of 0.5 Ω mm has been achieved by partially etching the AlN barrier layer using a chlorine-based plasma dry-etch prior to ohmic contact metallization. For thin GaN-capped AlN/GaN heterostructures, we find it is necessary to remove the GaN cap in the vicinity of the contact metal in order to obtain a linear current–voltage relationship. We compare our results of the pre-metallization etched contacts to those without an etch as well as to results reported in the literature.

Effect of interface states on sub-threshold response of III-V MOSFETs, MOS HEMTs and tunnel FETs

Abstract: The effect of interface states on the current–voltage characteristics in the sub-threshold region of three different types of III–V based transistor architectures has been studied using a drift–diffusion based numerical simulator. Experimentally extracted interface state density profile is included in the simulation to analyze their effect on the sub-threshold response of InGaAs based MOSFETs, MOS HEMTs and tunnel FETs. Based on the Fermi-level position at the oxide/semiconductor interface and the corresponding interface state density (Dit), the sub-threshold response for the three devices can vary, with tunnel FETs having the least sub-threshold degradation due to Dit.

The effect of photodiode shape on charge transfer in CMOS image sensors

Abstract: The output signal of a CMOS image sensor is derived from the electrons generated by light incident on the pinned photodiode in each pixel. The output voltage depends on the transfer of the signal electrons from the pinned photodiode to the readout node. In large photodiodes it becomes difficult to fully extract the generated electrons because of the reduction in lateral electric field that pushes the electrons to the transfer transistor. To enhance the transfer, a triangular shaped photodiode was proposed which increases the lateral electric field applied to the photo generated electrons. Compared with a conventional rectangular shaped pixel, the electrons are extracted more easily in a triangular shape since the narrow tail end forms an increased potential gradient. A VGA type image sensor chip showed that the triangular photodiode had 50% higher output voltage than a conventional rectangular photodiode. It was verified that the output voltage is enhanced more by the electric force than the light receiving area. The noise due to the residual electrons was not seen in the image acquired from image sensor having triangular photodiode.

Operational upsets and critical new bit errors in CMOS digital inverters due to high power pulsed electromagnetic interference

Abstract: The effects of high power pulsed electromagnetic interference from high power microwave sources on static and dynamic operation of CMOS digital inverters, is reported. The output voltage and current transfer characteristics of 1.5 μm and 0.5 μm CMOS inverters were measured under pulsed interference at frequencies of 1 GHz and 3 GHz. New bit-flip errors have been identified to occur at or below the threshold voltage of the n-channel MOSFETs in the first stage of the inverters, resulting in propagating errors. Errors were also observed for above threshold, which propagated in subsequent stages either as noise or as bit-flip errors when exceeding the device noise margins. Time domain measurements showed that bit-flip error rate increased with peak power for the same average power. The current transfer characteristics showed significantly increased inverter output currents at the ON, switching, and OFF states with higher peak power. It is shown that peak power is one of the critical parameters for the increased threat level of pulsed interference.

Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides

Abstract: This paper presents a detailed experimental study of the electrical characteristics of long-channel ultra-thin body SOI MOSFETs with standard and thin buried oxides and high-k gate dielectric, using an analysis of the transconductance, gate-to-channel capacitance and mobility behaviors at different back-gate biases. The emphasis is on the evolution of the effective mobility when shifting the conduction channel in the film from front to back interface, and on the comparison between the two BOX thicknesses. It is found that the back-channel mobility significantly exceeds the front-channel mobility, which is presumably related to strongly different Coulomb scattering at the two interfaces, being in agreement with previously published experimental studies. Furthermore, the back-channel mobility is found to be the same for thick and thin BOX. This strongly suggests that BOX thinning does not degrade the quality of the back interface. The observed effect of much higher back-channel mobility, which is retained for the thin BOX, could find application for the additional improvement of the device performance, when adjusting the threshold voltage via back-gate bias. Adequate mobility interpretation is then required as a varying combination of front and back-channel mobilities.

Fabrication of normally-off mode GaN and AlGaN/GaN MOSFETs with HfO2 gate insulator

Abstract: We have fabricated III-nitride metal-oxide field effect transistors (MOSFETs) using high- k HfO 2 as a gate oxide. Two types of MOSFETs were studied; GaN MOSFETs and AlGaN/GaN MOSFETs. In the case of GaN MOSFETs, the maximum transconductance of 45 mS/mm has been obtained. This is seven times larger than the best-reported value, to our knowledge, for the normally-off GaN MOSFETs with SiO 2 gate oxide. In order to improve the performance of the device, AlGaN/GaN MOSFETs in which high-quality AlGaN/GaN heterointerface is used as a channel have been fabricated. The maximum transconductance and drain current were as high as 160 mS/mm and 840 mA/mm, respectively.