FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

Charge carrier control is a key issue in the development of electronic functions of semiconductive materials. Beyond the simple enhancement of conductivity, high charge carrier accumulation can realize various phenomena, such as chemical reaction, phase transition, magnetic ordering, and superconductivity. Electric double layers (EDLs), formed at solid-electrolyte interfaces, induce extremely large electric fields. This results in a high charge carrier accumulation in the solid, much more effectively than solid dielectric materials. In the present review, we describe recent developments in the field-effect transistors (FETs) with gate dielectrics of ionic liquids, which have attracted much attention due to their wide electrochemical windows, low vapor pressures, and high chemical and physical stability. We explain the capacitance effects of ionic liquids, and describe the various combinations of ionic liquids and organic and inorganic semiconductors that are used to achieve such effects as high transistor performance, insulator-metal transitions, superconductivity, and ferromagnetism, in addition to the applications of the ionic-liquid EDL-FETs in logic devices. We discuss the factors controlling the mobility and threshold voltage in these types of FETs, and show the ionic liquid dependence of the transistor performance.

Electric-double-layer field-effect transistors with ionic liquids.

We report on a lateral interband tunneling transistor, where the source and drain form a heavily doped lateral pn junction in a thin Si film on a silicon-on-insulator (SOI) substrate. The transistor action results from the control of the reverse-bias tunneling breakdown under drain bias VD by a gate voltage VG. We observe gate control over tunneling drain current ID at both polarities of VG with negligible gate leakage. Systematic ID(VG,VD) measurements, together with numerical device simulations, show that in first approximation ID depends on the maximum junction electric field Fmax(VG,VD). Excellent performance is hence predicted in devices with more abrupt junctions and thinner SOI films. The device does not have an inversion channel and is not subject to scaling rules of standard Si transistors.

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Lateral interband tunneling transistor in silicon-on-insulator

Effect of gate engineering in double-gate MOSFETs for analog/RF applications

This paper reviews and compares predictions of the Dutta-Horn model of low-frequency excess ( ${\bf 1}/\mbi{f}$ ) noise with experimental results for thin metal films, MOS transistors, and GaN/AlGaN high-electron mobility transistors (HEMTs). For metal films, mobility fluctuations associated with carrier-defect scattering lead to ${\bf 1}/\mbi{f}$ noise. In contrast, for most semiconductor devices, the noise usually results from fluctuations in the number of carriers due to charge exchange between the channel and defects, usually at or near a critical semiconductor/insulator interface. The Dutta-Horn model describes the noise with high precision in most cases. Insight into the physical mechanisms that lead to noise in microelectronic materials and devices has been obtained via total-ionizing-dose irradiation and/or thermal annealing, as illustrated with several examples. With the assistance of the Dutta-Horn model, measurements of the noise magnitude and temperature and/or voltage dependence of the noise enable estimates of the energy distributions of defects that lead to ${\bf 1}/\mbi{f}$ noise. The microstructure of several defects and/or impurities that cause noise in MOS devices (primarily O vacancies) and GaN/AlGaN HEMTs (e.g., hydrogenated impurity centers, N vacancies, and/or Fe centers) have been identified via experiments and density functional theory calculations.

$1/f$ Noise and Defects in Microelectronic Materials and Devices

The operation of 1-3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, a large influence of substrate depletion underneath the buried oxide, the absence of drain current transients, and degradation in electron mobility are typical effects in these ultra-thin MOSFETs. The comparison of SG and DG configurations demonstrates the superiority of DG-MOSFETs: ideal subthreshold swing and remarkably improved transconductance (consistently higher than twice the value in SG-MOSFETs). The experimental data and the difference between SG and DG modes is explained by combining classical models with quantum calculations. The key effect in ultimately thin DG-MOSFETs is volume inversion, which primarily leads to an improvement in mobility, whereas the total inversion charge is only marginally modified.

T. Ernst

Papers

Ultimately thin double-gate SOI MOSFETs