The performance of electronic and optoelectronic devices based on two-dimensional layered crystals, including graphene, semiconductors of the transition metal dichalcogenide family such as molybdenum disulphide (MoS2) and tungsten diselenide (WSe2), as well as other emerging two-dimensional semiconductors such as atomically thin black phosphorus, is significantly affected by the electrical contacts that connect these materials with external circuitry. Here, we present a comprehensive treatment of the physics of such interfaces at the contact region and discuss recent progress towards realizing optimal contacts for two-dimensional materials. We also discuss the requirements that must be fulfilled to realize efficient spin injection in transition metal dichalcogenides.

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Electrical contacts to two-dimensional semiconductors

A high-quality junction between graphene and metallic contacts is crucial in the creation of high-performance graphene transistors. In an ideal metal-graphene junction, the contact resistance is determined solely by the number of conduction modes in graphene. However, as yet, measurements of contact resistance have been inconsistent, and the factors that determine the contact resistance remain unclear. Here, we report that the contact resistance in a palladium-graphene junction exhibits an anomalous temperature dependence, dropping significantly as temperature decreases to a value of just 110 ± 20 Ω µm at 6 K, which is two to three times the minimum achievable resistance. Using a combination of experiment and theory we show that this behaviour results from carrier transport in graphene under the palladium contact. At low temperature, the carrier mean free path exceeds the palladium-graphene coupling length, leading to nearly ballistic transport with a transfer efficiency of ~75%. As the temperature increases, this carrier transport becomes less ballistic, resulting in a considerable reduction in efficiency.

https://researcher.watson.ibm.com/researcher/files/us-vperebe/graphene_contact.pdf

The origins and limits of metal–graphene junction resistance

We present the results of a thorough study of wet chemical methods for transferring chemical vapor deposition grown graphene from the metal growth substrate to a device-compatible substrate. On the basis of these results, we have developed a “modified RCA clean” transfer method that has much better control of both contamination and crack formation and does not degrade the quality of the transferred graphene. Using this transfer method, high device yields, up to 97%, with a narrow device performance metrics distribution were achieved. This demonstration addresses an important step toward large-scale graphene-based electronic device applications.

Toward Clean and Crackless Transfer of Graphene

As silicon-based electronics approach the limit of improvements to performance and capacity through dimensional scaling, attention in the semiconductor field has turned to graphene, a single layer of carbon atoms arranged in a honeycomb lattice. Its high mobility of charge carriers (electrons and holes) could lead to its use in the next generation of high-performance devices. Graphene is unlikely to replace silicon completely, however, because of the poor on/off current ratio resulting from its zero bandgap. But it could be used to improve silicon-based devices, in particular in high-speed electronics and optical modulators.

A role for graphene in silicon-based semiconductor devices

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Graphene with a high carrier mobility of more than 10,000 cm2/Vs on SiO 2 has attracted much attention as a promising candidate of future high-speed transistor materials. The contact resistance (RC) between graphene and metal electrodes is crucially important for achieving potentially high performance of graphene from both physics and practical viewpoints. This paper discusses metal/graphene contact properties by separating from the intrinsic conduction of graphene.

Metal/graphene contact as a performance Killer of ultra-high mobility graphene analysis of intrinsic mobility and contact resistance

We propose a two-step oxidation with high-pressure oxidation and low-temperature oxygen annealing to form ideal Ge/GeO2 stacks based on thermodynamic and kinetic control. The capacitance-voltage (C-V) characteristics of Ge/GeO2 MISCAPs with two-step oxidation revealed significant improvements of electrical properties, and the interface states density (Dit) estimated with a low-temperature conductance method that was below 1011 eV-1 cm-2 near the midgap. On the basis of our understanding of Ge oxidation, we demonstrated very high electron mobility in Ge n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) that exceeded the universal mobility in Si-MOSFETs. The peak electron mobility in Ge n-MOSFETs with the two-step oxidation was 1100 cm2/V · s in the Al/GeO2/Ge stack. This was achieved by taking care of the Ge/GeO2 channel interface. Since we clarified that mobility was still limited by the remaining extrinsic scattering sources, the present results promise much higher performance Ge complementary metal-oxide-semiconductor.

High-Electron-Mobility $\hbox{Ge/GeO}_{2}$ n-MOSFETs With Two-Step Oxidation

We have systematically investigated Ge interface passivation methods, and the highest electron (1920 cm2/Vs) and hole mobility (725 cm2/Vs) have been demonstrated by dramatic reduction of D it through the collaboration of self-passivation and valency passivation. In Si passivation, it is found that Si contributes to the upper half (worse) and lower one (better) in the bandgap differently. This study strongly suggests us that high performance Ge CMOS is really feasible.

Ge MOSFETs performance: Impact of Ge interface passivation

Based on the understanding of kinetic views of GeO desorption from GeO 2 /Ge stacks, thermodynamic control of the qualities of both GeO 2 films and GeO 2 /Ge interfaces was demonstrated. It was proposed to characterize the effects of GeO desorption on GeO 2 by the optical absorption. In addition, MIS band alignment was also discussed from the viewpoint of the effects of metal-GeO 2 interaction at the top interface.

Comprehensive study of GeO 2 oxidation, GeO desorption and GeO 2 -metal interaction -understanding of Ge processing kinetics for perfect interface control-

Thermal oxidation kinetics of Ge was investigated by the 18O tracing study and re-oxidation experiments of the SiO2/GeO2 stacked oxide-layer. The results suggest that Ge oxidation kinetics is completely different from that expected from the Deal-Grove model and that Ge is oxidized by GeO2 on Ge instead of O2 at the interface. This oxidation process forms large amounts of oxygen vacancies in GeO2, which facilitate the diffusion of oxygen atoms in GeO2. This means that oxygen atoms diffuse through GeO2 with an exchange type of process. Based on experimental results, a possible kinetics for Ge oxidation is discussed.

T. Nishimura

Papers

Metal/graphene contact as a performance Killer of ultra-high mobility graphene analysis of intrinsic mobility and contact resistance

High-Electron-Mobility $\hbox{Ge/GeO}_{2}$ n-MOSFETs With Two-Step Oxidation

Ge MOSFETs performance: Impact of Ge interface passivation

Comprehensive study of GeO 2 oxidation, GeO desorption and GeO 2 -metal interaction -understanding of Ge processing kinetics for perfect interface control-

Thermal oxidation kinetics of germanium