Historical developments of the metal-oxide-semiconductor field-effect transistor (MOSFET) during the last 60 years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triode structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon. MOSFET in 1960. A survey is then made of the milestones of the past 30 years leading to the latest submicron silicon logic CMOS (complementary MOS) and BICMOS (bipolar-junction transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. The status of the submicron lithographic technologies is summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. The use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. >

Evolution of the MOS transistor-from conception to VLSI

The Silicon and Aluminum Metal Oxide Semiconductor (SAMOS) technology is presented as a high-yield, low-cost process to make one-device-cell random access memories. The characteristics of the process are a multilayer dielectric gate insulator (oxide-nitride), a p-type polysilicon field shield, and a doped oxide diffusion source. Added yield-enhancing features are backside ion implant gettering, dual dielectric insulators between metal layers, and circuit redundancy. A family of chips is produced using SAMOS, ranging from 18K bits to 64K bits. System features such as on-chip data registers are designed on some chips. The chip technology is merged with "flip-chip" packaging to provide one-inch-square modules from 72K bits through 512K bits, with typical access times from 90 ns to 300 ns.

A silicon and aluminum dynamic memory technology

Electron beam lithography is a rapidly maturing technology that has opened the realm of submicron design to the semiconductor device and circuit designer. This improved pattern resolution has already yielded devices and circuits exhibiting higher density, higher operating frequency, and lower operating power than has been possible with other lithography methods. This paper discusses electron beam lithography and the devices and circuits that have been fabricated with this technology.

Electron Beam Lithography

It is argued that the cost of manufacturing submicron, ultra-large-scale integration (ULSI) integrated circuits (ICs) (which is scaling upward at least in inverse proportion to the downward scaling of device feature sizes) is driven by a parameter budget crisis associated with the technological and complexity limits of IC design and fabrication. This budget crisis is defined for technologies associated with patterning, mechanical control, thermal treatments, particulates and contamination, defects, electrical parameters, and manufacturing, R&D priorities for silicon ULSI are identified and quantified, and the potential impact of some recent research results is discussed. It is pointed out that the R&D agenda to deal with the ULSI manufacturing budget crisis is enormous, and the semiconductor industry cannot perform all of it. Since the time for transferring new developments into production tools and technologies is five to seven years, it is concluded that critical funding decisions need to be made now for ULSI manufacturing science breakthroughs by the turn of the century. >

Challenges to manufacturing submicron, ultra-large scale integrated circuits

Challenges to Manufacturing Submicron, U Itra-Large Scale Integrated Circuits

This paper discusses the fabrication of 1 µm minimum linewidth FET polysilicon-gate devices and circuits. These were designed for the tight dimensional ground rules (resolution, linewidth control, and overlay) achievable using direct wafer write scanning electron-beam lithography with individual chip registration. The present work focuses on vector-scan electron-beam technology and processing, while other papers in this series discuss other aspects of the work. Different types of 1 µm MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system which performs table stepping, registration to fiducial marks, and pattern writing in a vector scan mode (on an individual shape basis) with control of exposure dose for individual shapes. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.

1 &#181;m MOSFET VLSI technology: Part VI&#8212;Electron-beam lithography

We describe the fabrication of 1 micron minimum linewidth FET polysilicon devices and circuits. These were designed for the tight dimensional groundrules achievable using direct wafer write scanning electron beam lithography. This paper emphasizes the vector-scan electron beam technology and processing, while other papers in this conference(1) discuss other aspects of the work. Different types of 1 micron FET chips were written on 57mm Si wafers using a totally automated electron beam system(2) which performs table stepping, registration to fiducial marks, and pattern writing in a vector scan mode (individual shape basis) with control of exposure dose for individual shapes. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance jumps between shapes. A novel two-layer positive resist system has been developed to achieve reproducible lift-off profiles over topography and better linewidth control (typically <0.1 micron). A level to level registration accuracy groundrule of 0.3 micron has been satisfied with achievement of typical alignment of 0.1-0.2 microns between any two levels.

Electron beam lithography for 1 micron FET logic circuit fabrication

For pt.V see ibid., vol.SC14, no.2, p.275 (1979). The authors discuss the fabrication of 1 /spl mu/m minimum linewidth FET polysilicon-gate devices and circuits, with emphasis on vector-scan electron-beam technology and processing. Different types of 1 /spl mu/m MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.

T.P. Donohue

Papers

1 µm MOSFET VLSI technology: Part VI—Electron-beam lithography

Electron beam lithography for 1 micron FET logic circuit fabrication

1 /spl mu/m MOSFET VLSI technology. VI. Electron-beam lithography

T.P. Donohue

Papers

1 &#181;m MOSFET VLSI technology: Part VI&#8212;Electron-beam lithography

Electron beam lithography for 1 micron FET logic circuit fabrication

1 /spl mu/m MOSFET VLSI technology. VI. Electron-beam lithography

1 µm MOSFET VLSI technology: Part VI—Electron-beam lithography