We fabricate and characterize dual-gated graphene field-effect transistors (FETs) using Al2O3 as top-gate dielectric. We use a thin Al film as a nucleation layer to enable the atomic layer deposition of Al2O3. Our devices show mobility values of over 8,000 cm2/Vs at room temperature, a finding which indicates that the top-gate stack does not significantly increase the carrier scattering, and consequently degrade the device characteristics. We propose a device model to fit the experimental data using a single mobility value.

Realization of a High Mobility Dual-gated Graphene Field Effect Transistor with Al2O3 Dielectric

We fabricate and characterize dual-gated graphene field-effect transistors using Al2O3 as top-gate dielectric. We use a thin Al film as a nucleation layer to enable the atomic layer deposition of Al2O3. Our devices show mobility values of over 8000 cm2/V s at room temperature, a finding which indicates that the top-gate stack does not significantly increase the carrier scattering and consequently degrade the device characteristics. We propose a device model to fit the experimental data using a single mobility value.

Realization of a high mobility dual-gated graphene field-effect transistor with Al2O3 dielectric

This review encompasses the application of the scanning electron microscope to the study and characterization of semiconductor materials and devices by the Electron Beam Induced Conductivity (EBIC) method. In this technique, the charge carriers generated by the electron beam of the microscope are collected by an electric field within the material and sensed as a current in an external circuit. When employed as the video signal of the SEM, this collected current image reveals inhomogeneities in the electrical properties of the material. The technique has been used to determine carrier lifetime, diffusion length, defect energy levels, and surface recombination velocities. Charge collection images reveal the location of p‐n junctions, recombination sites such as dislocations and precipitates, and the presence of doping level inhomogeneities. Both the theoretical foundation and the practical aspects of these effects are discussed in a tutorial fashion in this review.

Charge collection scanning electron microscopy

A review of the sputtered film stress literature shows that the intrinsic stress can be tensile or compressive depending on the energetics of the deposition process. Modeling studies of film growth and extensive experimental evidence show a direct link between the energetics of the deposition process and film microstructure, which in turn determines the nature and magnitude of the stress. The fundamental quantities are the particle flux and energy striking the condensing film, which are a function of many process parameters such as pressure (discharge voltage), target/sputtering gas mass ratio, cathode shape, bias voltage, and substrate orientation. Tensile stress is generally observed in zone 1-type, porous films and is explained in terms of the grain boundary relaxation model, whereas compressive stress, observed in zone T-type, dense films, is interpreted in terms of the atomic peening mechanism. Modeling of the atomic peening mechanism and experimental data indicate that the normalized moment...

Intrinsic stress in sputter-deposited thin films

Mechanical stress in interconnections is a problem of growing importance in VLSI devices. The origins of this stress are discussed, and a measurement technique based on the determination of wafer curvature with a laser scanning device is described. The changes in stress observed during thermal cycles are interpreted quantitatively in terms of a simple model of elastic and plastic strain in the metal. The effects of changes in deposition conditions, film composition, and film structure are discussed.

Measurement and Interpretation of stress in aluminum-based metallization as a function of thermal history

Nonplanar silicon surfaces were prepared and oxidized at 900°–1100°C and the oxide morphology was studied by transmission electron microscopy of thin sections. A 30% decrease in oxide thickness at silicon step edges following 900° and 950°C wet oxidation is attributed to the effect of locally compressive intrinsic stress within the oxide on the solubility of oxygen. Oxidation inhibition becomes less at higher temperatures due to the relief of stress (during growth) by viscous flow of the oxide.

The Oxidation of Shaped Silicon Surfaces

The temperature dependence of stresses in aluminum films on oxidized silicon substrates

Arsenic‐ and antimony‐implanted silicon wafers have been annealed by a cw Ar ion laser. Glancing‐angle Rutherford backscattering and transmission electron and optical microscopy measurements indicate that the mechanism for recrystallization is one of thermal solid‐phase regrowth from the underlying crystalline‐amorphous interface. No implant redistribution is observed.

Solid-phase epitaxy of implanted silicon by cw Ar ion laser irradiation

It is shown that MOS–LSI devices can be satisfactorily metallized with tungsten thin films using the rf-diode sputtering technique. The apparatus used consisted of a roots-blower and a Vacion pumped belljar system equipped with an 8-in. diam CVD W-cathode and a W-substrate table (anode) to which a dc bias could be applied. The control substrates were oxidized silicon wafers in which the back-oxide was removed to facilitate proper application of the bias. The effect of sputtering power (200–400 W) and of substrate bias (−200−+250 V) was studied on the deposition rate, substrate temperature, and various properties of the film such as electrical resistivity, stress, impurity concentration, constitution, and microstructure. The present process of W-film depostition has been found to offer several advantages. Low-power and low-voltage operation results in high quality MOS-compatible W-films. Substrate heating during the sputter deposition is kept to a minimum, thereby eliminating any undesirable metallurgical ...

Tungsten metallization for LSI applications

We have studied the Si‐SiO2 interface of a Si‐MOSFET (metal‐oxide‐semiconductor field‐effect transistor) on a (911) surface by high‐resolution electron microscopy. The interface was viewed edge‐on parallel to [011] and the Si crystal lattice was directly resolved. The image shows the interface to be smooth to within 4 A and contains a possible indication of a transition layer (∼10 A) of nonstoichiometric oxides.

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T. T. Sheng

Papers

The Oxidation of Shaped Silicon Surfaces

The temperature dependence of stresses in aluminum films on oxidized silicon substrates

Solid-phase epitaxy of implanted silicon by cw Ar ion laser irradiation

Tungsten metallization for LSI applications

A high‐resolution electron microscopy study of the Si‐SiO2 interface