Remote home monitoring via wearables is rapidly gaining popularity, thanks to ever more complex vital signs recording and data analytics that are embedded into single devices. True system-on-chips (SoCs) push the envelope of power and form factor, while wearables are becoming more common-place, novel health sensing paradigms appear. Non-contact sensing technologies enable vital signs sensing without requiring any physical contact with the human body. This article reviews existing multiple-modality bio-signal recording and processing SoCs, circuit techniques for individual bio-signal readout channels including electrocardiography (ECG), Electroencephalography (EEG), Bio-impedance (BioZ), photoplethysmography (PPG), and non-contact sensing with high user comfort. The state-of-the-art wearable sensor interfaces and systems together with future development trends are provided.

Wearable Multiple Modality Bio-Signal Recording and Processing on Chip: A Review

Total-ionizing-dose (TID) effects and low-frequency noise are evaluated in advanced bulk nMOS and pMOS FinFETs with SiO2/HfO2 gate dielectrics. Otherwise identical devices built with and without through-silicon via (TSV) integration exhibit threshold voltage shifts of less than 25 mV and changes in maximum transconductance of less than 1% up to 2 Mrad(SiO2). TSV integration negligibly impacts threshold shifts and degradation of subthreshold swing and $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratios. Similar low-frequency noise magnitudes and frequency dependencies are observed before and after TID irradiation for each device type. Effective densities of the near-interfacial electron traps responsible for the noise in the nMOS devices increase as the surface potential moves toward midgap, while effective densities of the hole traps that cause the noise in the pMOS devices increase as the surface potential moves toward the valence band edge.

Impacts of Through-Silicon Vias on Total-Ionizing-Dose Effects and Low-Frequency Noise in FinFETs

Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This article reports the ${I-V}$ , programming, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.

/pdf/generation-of-stdp-with-non-volatile-tunnel-fet-memory-for-26id9igo4i.pdf

Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks

In this paper, a new circuit model is proposed to simulate plasma-induced damage (PID). It includes the two sheaths of the plasma, the blocking capacitor, and the RF power source coupled with the victim device. As a result, this model accounts for both the ac behavior of the plasma and the local voltage imbalance induced by differences in shading factors. The advantage of this approach, compared with the previous works, is that it can yield the waveform impinged by the plasma on the transistor gate, which is known to influence the amount of reliability degradation experienced by the device. Finally, this model is also utilized to elucidate the impact of a parasitic capacitance connected to the transistor gate on the extent of the PID inflicted on the victim device.

Full-Loop Equivalent Circuit Model for Plasma-Induced Damage Simulation

Retinal prosthesis is a promising treatment for vision degeneration. However, clinical experiments show that the patients can only recognize several grayscales at low resolution with electrical stimulation. This paper proposes a retinal prosthesis chip with binarization and edge detection functions to maximize the brightness difference and reduce redundant information. The binarization operation is designed as a column-parallel processing element for saving space. Moreover, the fill factor achieves 50.79% by separating the sensor and stimulator into different chips. Finally, the SPICE simulator verified the effectiveness of the proposed circuit, which achieves an FoM of 110nW/(frame·pixel). 

3D-stacked retinal prosthesis chip with binary image capture and edge detection functions for human visual restoration

Mixed-signal 3D-ICs have a stacked structure of digital and analog circuit chips. In this study, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC. The noise propagation via through-silicon vias (TSVs) was measured, with a ring-oscillator as a noise source. For a comprehensive investigation, TSV-liner interface states were evaluated along the depth direction using unique multiwell-structured TSVs and a charge-pumping method. It was considered that the interface traps and nonconformal thickness of the TSV liner increased the noise propagation among stacked chips.

/pdf/investigation-of-tsv-liner-interface-with-multiwell-16pmnegnfl.pdf

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

https://iopscience.iop.org/article/10.35848/1347-4065/ab6867/pdf

Symmetric and asymmetric spike-timing-dependent plasticity function realized in a tunnel-field-effect-transistor-based charge-trapping memory

3D-IC (3D-stacked integrated circuit) requires lots of through-Si vias (TSVs) and metal microbumps for electrical connection among stacked LSI chips to realize higher performance beyond 2D-IC. However, plasma etching process for via-last backside TSV formation could damage many transistors used in the 3D-IC. In this study, plasma-induced charge-up damages on transistor characteristics during viahole etching have been investigated using test structures flipchip bonded on Si interposer. Additionally, antenna rules for the 3D-IC layout and process design were also mentioned.

Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV

We have investigated the effect of plasma damage in TSV formation on MOSFET characteristics to discuss the new antenna rule for the 3D IC design. An IC chip for evaluation was bonded to Si interposer with Cu/Sn microbumps at 280°C for 190 sec and thinned to 50-m thickness. Via holes through a Si substrate for TSV are formed by ICP-RIE at the backside surface of the IC chip. Diameter and number of via holes are 25 m and 1, 6, 11, and 21, respectively. These via holes interconnected the first metal which interconnect the gate metal of MOSFET fabricated on IC chip. We measured the Id-Vg characteristics of the MOSFET before and after via-holes formation. The measurement results show no significant change even after via-holes formation. It is indicated that the via-hole-etching process doesn’t affect MOSFET characteristics, because the gate capacitance of MOSFET is much smaller than parasitic capacitance of the first metal.

Takafumi Fukusima

Papers

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

Symmetric and asymmetric spike-timing-dependent plasticity function realized in a tunnel-field-effect-transistor-based charge-trapping memory

Impact of deep-via plasma etching process on transistor performance in 3D-IC with via-last backside TSV

Investigation of the Plasma Damage by Etching Process for TSV Formation in Via-last Backside-via 3D IC