A three-dimensional stacked IC (3D IC) is a one of the promising structures for enhancing IC performances. A 3D IC consists of several materials such as a Si substrate, metal for through Si via (TSV) and microbump, organic adhesive called the underfill, and so on. These materials generate a coefficient of thermal expansion (CTE) mismatch. On the other hand, heat is generated in the Si substrate during circuit operation and in the environment outside 3D IC, for example. Both the CTE mismatch and heat generation induce local stress caused by expansion of the underfill injected around metal microbumps. In this paper, we report our investigation results of the effects of adhesive expansion on transistor performances by finite element method (FEM) simulation and measurement of transistor characteristics.

http://iopscience.iop.org/article/10.7567/JJAP.55.04EC03/pdf

Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC

Total-ionizing-dose (TID) effects and low-frequency noise are evaluated in advanced bulk nMOS and pMOS FinFETs with SiO2/HfO2 gate dielectrics. Otherwise identical devices built with and without through-silicon via (TSV) integration exhibit threshold voltage shifts of less than 25 mV and changes in maximum transconductance of less than 1% up to 2 Mrad(SiO2). TSV integration negligibly impacts threshold shifts and degradation of subthreshold swing and $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratios. Similar low-frequency noise magnitudes and frequency dependencies are observed before and after TID irradiation for each device type. Effective densities of the near-interfacial electron traps responsible for the noise in the nMOS devices increase as the surface potential moves toward midgap, while effective densities of the hole traps that cause the noise in the pMOS devices increase as the surface potential moves toward the valence band edge.

Impacts of Through-Silicon Vias on Total-Ionizing-Dose Effects and Low-Frequency Noise in FinFETs

Mixed-signal 3D-ICs have a stacked structure of digital and analog circuit chips. In this study, the effect of noise propagation from a digital circuit on an analog circuit was evaluated using an actual mixed-signal 3D-IC. The noise propagation via through-silicon vias (TSVs) was measured, with a ring-oscillator as a noise source. For a comprehensive investigation, TSV-liner interface states were evaluated along the depth direction using unique multiwell-structured TSVs and a charge-pumping method. It was considered that the interface traps and nonconformal thickness of the TSV liner increased the noise propagation among stacked chips.

/pdf/investigation-of-tsv-liner-interface-with-multiwell-16pmnegnfl.pdf

Investigation of TSV Liner Interface With Multiwell Structured TSV to Suppress Noise Propagation in Mixed-Signal 3D-IC

In this paper, a novel through-silicon via (TSV) structure, named partial coaxial TSV (PC-TSV), is proposed to suppress TSV-induced substrate noise. In this structure, the via is surrounded by a benzocyclobutene (BCB) layer, and a grounded metal ring placed at one end. The BCB layer can effectively reduce the leakage of the signal to the substrate, and the metal ring provides a low impedance path for the substrate noise. An equivalent RLGC model of this structure is also established, and it is verified by simulated result from CST. Then, the performance of PC-TSV is compared with that of the traditional TSV, TSV with p+ layer, and TSV with p+ guard ring. Analysis results in frequency domain indicate PC-TSV has a larger $\vert \text{S}_{21}\vert $ and less near-end crosstalk than other three structures. Additionally, analysis results in time domain show that the substrate voltage noise of this structure is obviously reduced compared with the TSV with p+ layer and TSV with p+ guard ring. Also, a feasible process flow for this structure is given and it is simpler than that for traditional coaxial TSV.

/pdf/partial-coaxial-through-silicon-via-for-suppressing-the-1b8aac881f.pdf

Partial Coaxial Through-Silicon via for Suppressing the Substrate Noise in 3-Dimensional Integrated Circuit

Abstract The design of organic/inorganic nanoparticles hybrids provides the great potential for the fabrication of γ-ray sensor systems. Herein, structural and dosimetric properties of the gamma irradiated poly vinyl acetate (PVAc) doped with cadmium telluride quantum dots (CdTe QDs) and graphene oxide (GO) nanoflakes have been investigated. Thioglycolic acid (TGA) capped water-soluble CdTe QDs and (GO) nanoflakes are synthesized and characterized. Then, CdTe QDs/GO/PVAc sensors were formed by post-depositing CdTe and GO over polymer matrix. The photophysical interactions between nanoparticles and organic polymer have been investigated using ohmic contact detectors with two gold coated electrodes. Real time dose rate information of the sensors such as sensitivity, repeatability, and the linearity of dose rate response were assessed. A wider photoelectric response range and wider gamma harvesting range were observed in the resultant hybrid gamma sensor at a standard bias voltage with respect to non-hybrid CdTe QDs/PVAc sensors.

Cadmium telluride quantum dots/graphene oxide/poly vinyl acetate (CdTe QDs/GO/PVAc) nanocomposite. A novel sensor for real time gamma radiation detection

Through-silicon-via (TSV) with polymer liner has attracted considerable attention because a polymer liner has low dielectric constant and good step coverage along the TSV surface, and it can suppress the TSV-induced stress. A polyimide (PI) is used as the polymer liner of TSV. However, there is a modulation of the parasitic capacitance present between TSV metal and Si substrate due to its high polar character. Therefore, in this paper, we propose the deployment of benzocyclobutene (BCB) and polybenzoxazole (PBO) which consists of no-polar groups as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structures with PI, BCB or PBO liners were fabricated and evaluated. In the case of BCB and PBO liners, remarkable hysteresis suppressions of the C-V curves was observed as compared to that of the PI liner. These results indicate that polar character is one of the most important characters for suppression of the capacitance modulation around TSVs and the detrapped-charge-induced signal noise. Then, BCB and PBO is a promising liner material of TSV for realizing highperformance and high-reliability three-dimensional stacked ICs.

Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs

Three dimensional IC (3D IC) has lots of through-Si vias (TSVs) and metal microbumps for electrical connection between stacked IC chips, and also has organic adhesives to enhance the mechanical strength of 3D IC. However, the coefficient of thermal expansion (CTE) mismatch between microbumps and organic adhesives generate the local bending stress in thinned IC chips. Therefore, Keep-Out-Zone (KOZ) for transistors must be considered in 3D IC design to eliminate characteristic fluctuations and degradations due to the local bending stress. In this study, for the first time, we evaluated the effects of low temperature curing adhesive on both the local bending stress and the resultant transistor characteristics for decrease in KOZ of 3D IC.

Minimization of Keep-Out-Zone (KOZ) in 3D IC by local bending stress suppression with low temperature curing adhesive

Through-Si-via (TSV) with polymer liner formation has attracted considerable attention because a polymer liner can be formed easily by spin coating, and it has low dielectric constant and good coverage along the TSV surface. A polyimide (PI) was used as the polymer liner of TSV. However, there is a high charge-trap density in the PI layer. These charge traps leads to modulation of the parasitic capacitance present between the TSV metal and the Si substrate. Therefore, in this paper, we propose the deployment of polybenzoxazole (PBO) as the polymer-liner material of TSV for minimizing the capacitance modulation. In this study, a metal-insulator-semiconductor capacitor with blind TSV structure was fabricated with PBO and PI liners. Further, capacitance-voltage (C-V) characteristics of the fabricated MOS capacitor were evaluated. In case of the PBO liner, remarkable suppression of the C-V curve shift was observed as compared to that of the PI liner. These results indicate that the PBO is a promising TSV liner material for realizing high-performance, high-reliability, and low-cost three-dimensional stacked ICs.

Minimized hysteresis and low parasitic capacitance TSV with PBO (polybenzoxazole) liner to achieve ultra-high-speed data transmission

Three-dimensional IC (3D IC) has attracted much attention as a promising method to enhance IC performance. Recently, great interests in mechanical reliability are increasing among 3D IC researchers for production of 3D IC. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive called underfill material. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE difference induces local bending stress in thinned IC chips. This local bending stress would affect transistor reliability in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we present design guideline of microbump layout which can suppress the local bending stress in 3D-stacked several thin IC chips.

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC

In this paper, a BCB (benzocyclobutene) resin is employed as a spin-on low-k polymer for TSV liner dielectrics. The BCB is perfectly covered on the sidewall of deep Si holes with a diameter of 8 μm and depth of 40 μm (aspect ratio: 5). The step coverage of the BCB is high and controllable by conditioning the spin rotation speed, spin-coating time, and deforming pressure to eliminate bubbles formed in the deep Si holes prior to spin-coating. Cu-TSVs with the BCB liner dielectric are successfully formed by the subsequent electro-less plated and electroplated Cu technologies. This cost-effective spin-on BCB technology will be applied to via-last TSV fabrication at low temperature below 250 C to give low-capacitance TSVs.

Yohei Sugawara

Papers

Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs

Minimization of Keep-Out-Zone (KOZ) in 3D IC by local bending stress suppression with low temperature curing adhesive

Minimized hysteresis and low parasitic capacitance TSV with PBO (polybenzoxazole) liner to achieve ultra-high-speed data transmission

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC

TSV liner dielectric technology with spin-on low-k polymer