Showing papers by "Tetsu Tanaka published in 2003"

A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory

Abstract: A capacitorless 1T DRAM cell using gate-induced drain leakage (GIRL) current for write operation was demonstrated for the first time. Compared with the conventional write operation with impact ionization current, write operation with GIDL current provides low-power and high-speed operation. The capacitorless 1T-DRAM is the most promising technology for high performance embedded DRAM LSI.

A 65 nm CMOS technology with a high-performance and low-leakage transistor, a 0.55 /spl mu/m/sup 2/ 6T-SRAM cell and robust hybrid-ULK/Cu interconnects for mobile multimedia applications

Abstract: This paper presents a 65 nm CMOS technology for mobile multimedia applications The reduction of interconnect capacitance is essential for high-speed data transmission and small power consumption for mobile core chips We have chosen a hybrid ULK structure which consists of NCS (nano-clustering silica; k=225) at the wire level and SiOC (k=29) at the via level Although NCS is a porous material, the NCS/SiOC structure has sufficient mechanical strength to endure CMP pressure and wire bonding Successfully fabricated 200 nm-pitch hybrid-ULK/Cu interconnects and a high-performance and low-leakage transistors meet the electrical targets from the circuit requirements Moreover, an embedded 6T-SRAM with a 055 /spl mu/m/sup 2/ small cell size has been achieved

Process and device technologies for high-performance 0.13 μm FCRAM

Abstract: We have developed a novel integration scheme for FCRAM cores using a high-dielectric capacitor technology and low-temperature process technology so we can scale the design rule towards 0.13 pm and improve device performance. Ru/Ta 2 O 5 /Ru capacitor technology, which can provide a dielectric constant as high as 70 and an SiO 2 -equivalent thickness of 0.7 nm, has been established combined with a robust cylinder electrode fabrication process using a TiN liner. A self-aligned storage-node contact fabrication process with low-temperature (600°C) Si 3 N 4 deposition improves the transistor performance by more than 10%. These technologies have been applied to a 0.13 μm-generation device, and the functionality of this device has been confirmed. Also, this paper demonstrates the scalability of these technologies to the 0.1 pm generation.

Highly Reliable Dynamic Random Access Memory Technology for Application Specific Memory with Dual Nitrogen Concentration Gate Oxynitrides Using Selective Nitrogen Implantation

Abstract: A polymetal dual gate dynamic random access memory (DRAM) for application specific memory (ASM) with dual nitrogen concentrated oxynitrides was developed for the first time. This technology uses selective nitrogen implantation performed just after gate oxidation. The nitrogen concentration of p-type metal oxide semiconductor (PMOS) in gate dielectric combined with nitrogen implantation and NO (nitric oxide) annealing is sufficiently high to suppress boron penetration, whereas that of the cell array transistor (cell-Tr) and n-type metal oxide semiconductor (NMOS) is sufficiently low to maintain the threshold voltage (Vth) without increasing the channel dosage by using only NO annealing.

Accurate transport modeling with 2D dopant profile effect in L/sub eff/ /spl sim/ 20 nm MOSFETs via inverse modeling

Abstract: To accurately consider 2D dopant profile effect, we have studied transport modeling by comparing nMOSFETs with indium or boron pocket implant. Our inverse modeling has successfully extracted their features of dopant profiles and DIBL effects. It has enabled us to evaluate that the generalized hydrodynamic model is highly reliable even in smaller MOSFETs down to L/sub eff/ /spl sim/ 20 nm.