Three parallel algorithms for classical molecular dynamics are presented. The first assigns each processor a fixed subset of atoms; the second assigns each a fixed subset of inter-atomic forces to compute; the third assigns each a fixed spatial region. The algorithms are suitable for molecular dynamics models which can be difficult to parallelize efficiently—those with short-range forces where the neighbors of each atom change rapidly. They can be implemented on any distributed-memory parallel machine which allows for message-passing of data between independently executing processors. The algorithms are tested on a standard Lennard-Jones benchmark problem for system sizes ranging from 500 to 100,000,000 atoms on several parallel supercomputers--the nCUBE 2, Intel iPSC/860 and Paragon, and Cray T3D. Comparing the results to the fastest reported vectorized Cray Y-MP and C90 algorithm shows that the current generation of parallel machines is competitive with conventional vector supercomputers even for small problems. For large problems, the spatial algorithm achieves parallel efficiencies of 90% and a 1840-node Intel Paragon performs up to 165 faster than a single Cray C9O processor. Trade-offs between the three algorithms and guidelines for adapting them to more complex molecular dynamics simulations are also discussed.

Fast parallel algorithms for short-range molecular dynamics

Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs

An overview over issues and findings in SiC power MOSFET reliability is given. The focus of this article is on threshold instabilities and the differences to Si power MOSFETs. Measurement techniques for the characterization of the threshold voltage instabilities are compared and discussed. Modeling of the threshold voltage instabilities based on capture–emission-time (CET) maps is a central topic. This modeling approach takes the complete gate bias/temperature history into account. It includes both gate stress polarities and is able to reproduce the short-term threshold variations during application-relevant 50-kHz bipolar ac-stress. In addition, the impact on circuit operation is discussed.

Review on SiC MOSFETs High-Voltage Device Reliability Focusing on Threshold Voltage Instability

The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

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Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

Remaining useful lifetime prediction and extension of Si power devices have been studied extensively. Silicon carbide (SiC) power devices have been developed and commercialized. Specifically, SiC mosfet s have been utilized for the next generation high-voltage, high-power converters with smaller size and higher efficiency, covering various mainstream applications, including photovoltaic systems, electric vehicles, solid-state transformers, and more electric ships and airplanes. However, the SiC-based devices have different failure modes and mechanisms compared with Si counterparts. Therefore, a comprehensive review is critical to develop accurate lifetime prediction and extension strategies for SiC power converter systems. The SiC power device component-level failure modes and mechanisms are first investigated. Different accelerated lifetime tests and component-level lifetime models are then compared. Power converter system-level offline lifetime modeling techniques and software tools are further summarized. Besides, the SiC power converter condition monitoring strategies and health indicators are surveyed. The online measurement challenges are also studied. Furthermore, the system-level lifetime extension strategies are reviewed. By integrating device physics, statistical modeling, reliability engineering, and mechanical engineering with power electronics, this article is intended to provide a comprehensive overview, address existing challenges, and unfold new research opportunities regarding the SiC power converter real-time lifetime prediction and extension.

Overview of Real-Time Lifetime Prediction and Extension for SiC Power Converters

This paper describes a novel SiC trench MOSFET concept. The device is designed to balance low conduction losses with Si-IGBT like reliability. Basic features of the static and dynamic performance as well as short circuit capability of the 45mΩ/1200 V CoolSiC™ MOSFET are presented. The favorable temperature behavior of the on-state resistance combined with a low sensitivity of the switching energies to temperature simplify the design-in. Long-term gate oxide tests reveal a very low extrinsic failure rate well matching the requirements of industrial applications.

Performance and ruggedness of 1200V SiC — Trench — MOSFET

The threshold voltage hysteresis in SiC power MOSFETs is rarely studied. This paper investigates the captureand emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias. We present a measurement technique which enables time-resolved measurement of the real ${V} _{\text {th}}$ during application-relevant bipolar ac high temperature gate stress. In addition, we use capture and emission time maps to explain the temperature dependence of $\Delta {\text V}_{\text {th}}$ after stress and are able to simulate $\Delta {\text V}_{\text {th}}$ after positive ac stress considering the full stress-history. Furthermore, we will show that the threshold voltage hysteresis has no harmful impact on switching operation in real applications.

Understanding BTI in SiC MOSFETs and Its Impact on Circuit Operation

Silicon carbide (SiC) based metal-oxide semiconductor-field-effect-transistors (MOSFETs) show excellent switching performance and reliability. However, compared to silicon devices the more complex properties of the semiconductor-dielectric interface imply some natural peculiarities in threshold voltage variation. This paper analyzes threshold voltage hysteresis effects, bias temperature instability effects (BTI) and their relevance for the switching behavior. Most of the effects can be understood by means of simple physical models and do not harm reliability and performance of the device. It turns out that the standard norm test and readout procedures typically used to characterize threshold voltage and threshold voltage drifts for Si devices are insufficient and need to be adapted for SiC MOSFETs in order to get reproducible and solid results.

Investigation of threshold voltage stability of SiC MOSFETs

Modeling of the threshold voltage instabilities in SiC power MOSFETs is difficult due to the fast recovery of ΔV th after positive and negative gate bias stress. This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature. We present a measurement technique which enables time-resolved measurements of the real Vth during application-relevant bipolar AC high temperature gate stress (HTGS). We use capture and emission time (CET) maps to model the temperature and voltage dependence of the ΔV th after positive as well as negative gate stress. In addition, we provide a complete modeling approach for the ΔV th after long-term AC stress considering the full stress-history. Furthermore, we present a very accurate model for the short-term hysteresis during a bipolar AC period and we show that the threshold voltage hysteresis has no harmful effect on switching operation in real applications.

Thomas Aichinger

Papers

Threshold voltage peculiarities and bias temperature instabilities of SiC MOSFETs

Performance and ruggedness of 1200V SiC — Trench — MOSFET

Understanding BTI in SiC MOSFETs and Its Impact on Circuit Operation

Investigation of threshold voltage stability of SiC MOSFETs

Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs