Showing papers by "Timo Hämäläinen published in 2005"

A survey of application distribution in wireless sensor networks

Abstract: Wireless sensor networks (WSNs) are deployed to an area of interest to sense phenomena, process sensed data, and take actions accordingly. Due to the limited WSN node resources, distributed processing is required for completing application tasks. Proposals implementing distribution services for WSNs are evolving on different levels of generality. In this paper, these solutions are reviewed in order to determine the current status. According to the review, existing distribution technologies for computer networks are not applicable for WSNs. Operating systems (OSs) and middleware architectures for WSNs implement separate services for distribution within the existing constraints but an approach providing a complete distributed environment for applications is absent. In order to implement an efficient and adaptive environment, a middleware should be tightly integrated in the underlying OS. We recommend a framework in which a middleware distributes the application processing to a WSN so that the application lifetime is maximized. OS implements services for application tasks and information gathering as well as control interfaces for the middleware.

Energy efficient wireless sensor network, node devices for the same and a method for arranging communications in a wireless sensor network

Abstract: A wireless sensor network, a node device thereof and a method for arranging communications therein are presented. A first frequency is used in wireless communication of information between a headnode and subnodes of a first cluster (103) using a time slotted channel access scheme. A headnode of a second cluster (113) known the first frequency and selects a second, different frequency for use in wireless communication of information within said second cluster (113) using a time slotted channel access scheme. The headnode of the first cluster (103) is informed about the second frequency selected for the second cluster (113). Information from the headnode of said first cluster (103) to the headnode of said second cluster (113) is communicated on said second frequency, using the same time slotted channel access scheme as other nodes in said second cluster (113).

Software and hardware prototypes of the IEEE 1588 precision time protocol on wireless LAN

Abstract: IEEE 1588 is a standard for precise clock synchronization for networked measurement and control systems in LAN environment. This paper presents the design and implementation of two IEEE 1588 prototypes for wireless LAN (WLAN). The first one is implemented using a Linux PC platform and a standard IEEE 802.11 WLAN with modifications to the network device driver. The second prototype is implemented using an embedded WLAN development board that implements the synchronization functionality using an embedded processor with programmable logic device (PLD) circuits. The measured results show that 1.1 ns average clock offset can be reached on HW based implementation, while Linux PC network driver enables 660 ns with a standard WLAN. Although WLAN is an extremely difficult environment for the synchronization, the results achieved with the prototype are fully comparable to those achieved with wired LAN implementations

UML 2.0 Profile for Embedded System Design

Abstract: The unified modeling language (UML) 2.0 is emerging in the area of embedded system design. This paper presents a new UML 2.0 profile - called TUT-profile - that introduces a set of stereotypes and design rules for an application, platform, and mapping. The profile classifies different application and platform components, and enables their parameterization. The TUT-profile concentrates on the structure of an application and platform, and utilizes standard UML 2.0 for the behavioral modeling. The application is seen as a set of active classes with an internal behavior. Correspondingly, the platform is seen as a component library with a parameterized presentation in UML 2.0 for each library component.

A parallel MPEG-4 encoder for FPGA based multiprocessor SoC

Abstract: A parallel MPEG-4 simple profile encoder for FPGA based multiprocessor system-on-chip (SoC) is presented. The goal is a computationally scalable framework independent of platform. The scalability is achieved by spatial parallelization where images are divided to horizontal slices. Slice coding tasks are mapped to the multiprocessor consisting of four soft-cores arranged into master-slave configuration. Also, the shared memory model is adopted where large images are stored in shared external memory while small on-chip buffers are used for processing. The interconnections between memories and processors are realized with our HIBI network. Our main contributions are the scalable encoder framework as well as methods for coping with limited memory of FPGA. The current software only implementation processes 6 QCIF frames/s with three encoding slaves. In practice, speed-ups of 1.7 and 2.3 have been measured with two and three slaves, respectively. FPGA utilization of current implementation is 59% requiring 24 207 logic elements on Altera Stratix EP1S40.

HIBI-based multiprocessor SoC on FPGA

Abstract: An FPGA offers an excellent platform for a system-on-chip consisting of intellectual property (IP) blocks. The problem is that IP blocks and their interconnections are often FPGA vendor dependent. Our HIBI (heterogeneous IP block interconnection) network-on-chip (NoC) scheme solves the problem by providing a flexible interconnection network and IP block integration with an open core protocol (OCP) interface. Therefore, IP components can be of any type: processors; hardware accelerators; communication interfaces; memories. As a proof of concept, a multiprocessor system with eight soft processor cores and HIBI is prototyped on FPGA. The whole system uses 36,402 logic elements, 2.9 Mbits of RAM, and operates at 78 MHz frequency on the Altera Stratix 1S40, which is comparable to other FPGA multiprocessors. The most important benefit is significant reduction of the design effort compared to system specific interconnection networks. HIBI also presents the first OCP compliant IP-block integration in FPGA.

Efficient hardware implementation of security processing for IEEE 802.15.4 wireless networks

Abstract: The IEEE 802.15.4 standard defines the medium access control and physical layer for low-rate, low-power wireless personal area networks (WPAN). As a number of WPAN applications require protected communications, the standard defines security procedures. Since the procedures typically consume most processing capacity in the limited 802.15.4 devices, efficient implementations are needed. As a solution, this paper presents a compact and energy-efficient hardware design, supporting all the security suites of the standard. Compared to typical WPAN processors, the presented FPGA prototype and the estimated ASIC implementation offer significantly higher performance and lower energy consumption. The FPGA throughput at the highest security level is 90 Mb/s and the energy consumption is 1/190 of an 8-bit microcontroller and 1/5 of an ARM9. The estimated energy consumption for the equivalent ASIC implementation is 1/10 of the FPGA prototype. In addition to 802.15.4, the hardware design supports all wireless technologies derived from the IEEE 802.11i security specification.

Using link layer information for improving vertical handovers

Abstract: In this paper we present a common triggering mechanism (cross-layer framework) and logic to gather link state and quality related information from the link layers of different access technologies. This information may he utilized by upper layer protocols and applications to react to changes of the link layer. Examples of such a utilization is movement detection, handover decision and application adaptation. The access technology dependent events and parameters, when necessary, are converted into access technology independent triggers and hints. The presented prototype architecture, link information provider (LIP), is currently tested with the VERHO vertical handover controller, which enables intelligent policy-based handover decisions according to several input parameters from the user, application, link layer, etc. Currently, LIP supports certain general link layer parameters, which can he gathered from the operating system and network interface drivers. The system is designed to be easily extended

Ultra low energy wireless temperature sensor network implementation

Abstract: Condition monitoring in buildings is one of the most potential and foreseen applications for wireless sensor networks (WSN). This paper presents the design and full scale prototype implementation of WSN for temperature monitoring. The prototypes are implemented using low power commercial of-the-shelf components including a 2.4 GHz radio, microcontrollers, and a custom TUTWSN communication protocol. A user application provides a graphical data analysis. Measurements indicate 183 muW to 390 muW average node power consumptions, as temperature is measured at 5 s intervals and data is multi-hop routed to a gateway. Predicted lifetime with two AA batteries is up to 4.9 years. In addition, experiments indicate that time accuracy is extremely important in hardware prototypes

Comments on "Winscale: an image-scaling algorithm using an area pixel Model"

Abstract: In the paper by Kim et al. (2003), the authors propose a new image scaling method called winscale. The presented method can be used for scaling up and down. However, scaling down utilizing the winscale concept gives exactly the same results as the well-known bilinear interpolation. Furthermore, compared to bilinear, scaling up with the proposed winscale "overlap stamping" method has very similar calculations. The basic winscale upscaling differs from the bilinear method.

Design of transport triggered architecture processors for wireless encryption

Abstract: Transport triggered architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this paper TTA processors for the RC4 and AES encryption algorithms of the new IEEE 802.11i WLAN security standard are designed. Special operations efficiently supporting the ciphers are developed. The TTA design flow is utilized for finding configurations with the best performance-size ratios. The size of the configuration supporting both the algorithms is 69.4 kgates and the throughput 100 Mb/s for RC4 and 68.5 Mb/s for AES at 100 MHz in the 0.13 /spl mu/m CMOS technology. Compared to commercial processors of the same wireless application domain, higher throughputs are achieved at significantly smaller area and lower clock speed, which also results in decreased energy consumption.

Block-level parallel processing for scaling evenly divisible images

Abstract: Image scaling is a frequent operation in medical image processing. This paper presents how two-dimensional (2-D) image scaling can be accelerated with a new coarse-grained parallel processing method. The method is based on evenly divisible image sizes which is, in practice, the case with most medical images. In the proposed method, the image is divided into slices and all the slices are scaled in parallel. The complexity of the method is examined with two parallel architectures while considering memory consumption and data throughput. Several scaling functions can be handled with these generic architectures including linear, cubic B-spline, cubic, Lagrange, Gaussian, and sinc interpolations. Parallelism can be adjusted independent of the complexity of the computational units. The most promising architecture is implemented as a simulation model and the hardware resources as well as the performance are evaluated. All the significant resources are shown to be linearly proportional to the parallelization factor. With contemporary programmable logic, real-time scaling is achievable with large resolution 2-D images and a good quality interpolation. The proposed block-level scaling is also shown to increase software scaling performance over four times.

Wireless sensor network implementation for industrial linear position metering

Abstract: This paper presents the design and performance measurements of a prototype wireless sensor network (WSN) for industrial linear position metering. Design includes two different prototype platforms and a user application. Prototypes combine energy efficient commercial off-the-shelf components including a 2.4 GHz radio, and the custom TUTWSN communication protocols resulting high robustness, autonomous operation and very low power consumption. The user application displays sensor data graphically and enables further data analysis. Measurements contain component power analysis and prototype performance measurements. The measurements indicate 200 /spl mu/W to 400 /spl mu/W average node power consumption, as 16-bit sample is measured with 1 Hz sample rate, and routed to a WSN gateway with 1 s latency per hop and 512 bps throughput between nodes. Predicted lifetime of implemented WSN is 2 months with a small rechargeable battery or over 2 years with two AA batteries.

Performance Modeling and Reporting for the UML 2.0 Design of Embedded Systems

Abstract: This paper presents a new performance modeling approach for the design of embedded real-time systems using UML 2.0. The approach responds to the lack of specific semantics for the performance modeling. The existing UML metamodel is extended by defining stereotypes to include the message latency and execution time in UML statecharts. The information may contain both the real-time constraints and measured values that are back-annotated to the UML model. Further, fully automated model transformation is used to visualize this information with sequence diagrams. The modeling approach has been prototyped with the UML implementation of a WLAN medium access control protocol. The experiences proved the approach to be practical and intuitive.

Energy optimized beacon transmission rate in a wireless sensor network

Abstract: Resource constrained wireless sensor networks (WSN) require an energy efficient medium access control (MAC) protocol that minimizes the radio active time (duty cycle). Time slotted MAC schemes provide lowest duty cycles by dividing time into consecutive data exchange and sleep periods. Synchronization for data exchange and network maintenance is achieved by exchanging beacons. For detecting changes in network topology, nodes periodically perform scanning during which beacons are received from neighbors. This is energy consuming, and the energy required equals to the transmission of thousands of packets. This paper shows that the energy consumption is mainly depending on the beacon transmission rate, and that an optimal rate is a function of three parameters: a network scanning interval, beacon transmission energy, and radio reception power. The optimal beacon transmission rate is derived for a TUTWSN prototype by power analysis and energy models. According to the analysis, the optimization decreases the average network energy consumption up to an order of magnitude. For the prototype, the optimal beacon transmission rate is 3.7 Hz, when network scanning is performed with 2 minutes intervals

Hybrid Algorithm for Mapping Static Task Graphs on Multiprocessor SoCs

Abstract: Mapping of applications on multiprocessor system-on-chip is a crucial step in the system design to optimize the performance, energy and memory constraints at the same time. The problem is formulated as finding solutions to an objective function of the algorithm performing the mapping and scheduling under strict constraints. Our solution is a new hybrid algorithm that distributes the computational tasks modeled as static acyclic task graphs The algorithm uses simulated annealing and group migration algorithms consecutively and it combines a non-greedy global and greedy local optimization techniques to have good properties of both ways. The algorithm begins as coarse grain optimization and moves towards fine grained optimization. As a case study we used ten 50-nodc graphs from the Standard Task Graph Set and averaged results over 100 optimization runs. The hybrid algorithm gives 8% better execution time on a system with four processing elements compared to simulated annealing. In addition, the number of iterations increased only moderately, which justifies the new algorithm in SoC design.

Multihop IEEE 802.11b WLAN Performance for VoIP

Abstract: This paper evaluates the performance of IEEE 802.11b WLAN for supporting multihop voice over IP (VoIP) service. Evaluation is carried out using the NS-2 network simulator and the mean opinion score (MOS) as a criteria for measuring the quality of a VoIP connection. The results show that the mean number of hops between a VoIP transmitter and receiver has the main effect on the number of calls with acceptable quality. On a small network where connections cause interference to each other already three hops cause problems. The mean number of hops can be decreased with a supporting access point (AP) infrastructure. Also the type of interfering traffic affects. The voice quality in VoIP is sensitive to transmission losses, and VoIP cannot compete equally with high data rate applications

Benchmarking mesh and hierarchical bus networks in system-on-chip context

Abstract: A simulation-based comparison scheme for on-chip communication networks is presented. Performance of the network depends heavily on the application and therefore several test cases are required. In this paper, generic synthesizable 2-dimensional mesh and hierarchical bus, which is an extended version of a single bus, are benchmarked in a SoC context with five parameterizable test cases. The results show that the hierarchical bus offers a good performance and area trade-off. In the presented test cases, a 2-dimensional mesh offers a speedup of 1.1x – 3.3x over hierarchical bus, but the area overhead is of 2.3x – 3.4x, which is larger than performance improvement.

Requirements for network-on-chip benchmarking

Abstract: This work presents the motivation, basic concepts, and requirements for benchmarking a network-on-chip (NoC). Currently there is practically no benchmark sets for NoC or the presented tools do not meet the requirements. The presented benchmarking method utilizes traffic generator with a dataflow models of the applications. Combined with transaction-level NoC, the abstract application model allows approximately 200/spl times/ speedup and on average 10% error in estimated runtime w.r.t. cycle-accurate HW/SW cosimulation without exposing the exact internal functionality of the application.

High abstraction level design and implementation framework for wireless sensor networks

Abstract: The diversity of applications, scarce resources, and large scale set demanding requirements for Wireless Sensor Networks (WSN). All requirements cannot be fulfilled by a general purpose WSN, but a development of application specific WSNs is needed. We present a novel WIreless SEnsor NEtwork Simulator (WISENES) framework for rapid design, simulation, evaluation, and implementation of both single nodes and large WSNs. New WSN design starts from high level Specification and Description Language (SDL) model, which is simulated and implemented on a prototype through code generation. One of the novel features is the back-annotation of measured values from physical prototypes to SDL model. The scalability and performance of WISENES have been evaluated with TUTWSN that is a very energy efficient new WSN. The results show only 6.7 percent difference between modeled and measured TUTWSN prototype energy consumption. Thus, WISENES hastens the development of WSN protocols and their evaluation in large networks.

Bandwidth allocation and pricing for telecommunications network

Abstract: The pricing of future network services should comparable to the service quality. In this paper we present a packet scheduling scheme which ensures bandwidth as a quality of service (QoS) requirement and optimizes revenue of the network service provider. We derive a closed form formula for updating the adaptive weights of a packet scheduler from a revenue-based optimization problem. The weight updating procedure is fast and independent on any assumption of the connections' statistical behavior. The algorithm is simulated and compared to constant weights with and without a call admission control (CAC) mechanism. Also, a mechanism for guaranteeing a minimum mean bandwidth for different service classes is presented as supplement to the CAC procedure.

Method, system and computer program product for producing, offering and executing recreational application programs

Abstract: Recreational application programs are offered for execution through players' terminals. Said recreational application programs involve at least one of playing and gambling. The system comprises an event model (301), which is a process adapted to represent a sequence of subevents in a target event (202, 203, 204) in real time. The system is adapted to offer the execution of a recreational application program through players' terminals as a response to an incident taking place in said event model (301).

A middleware for task allocation in wireless sensor networks

Abstract: Resource constrained platforms, dynamic nature, and complex applications set challenges to the development of wireless sensor networks (WSN). Sophisticated tasking and networking control is required in WSNs to reach lifetimes in order of years. This paper presents a WSN node middleware, which controls task allocation and WSN topology according to the current requirements of the application. The middleware uses a lightweight algorithm that balances communication and computation load between nodes. The discovering of resources and application tasks are comprised by a tuple space that selectively disperses information to nodes. The middleware has been implemented and evaluated in a wireless sensor network simulator (WISENES) that models resource usage and network operation accurately. The results show that in a static network configuration the obtained lifetime with our middleware is 6.8 times longer compared to an uncontrolled network while the increase in processing is negligible and the peek data memory usage increases by 11.6%. In a dynamically changing network the lifetime increases by a factor 3.9. Our middleware does not limit the applications and networks and improves the performance and predictability of WSNs significantly

Design and implementation of an enhanced security layer for Bluetooth

Abstract: This paper proposes a new Enhanced Security Layer (ESL) for Bluetooth. The security level is increased by replacing the encryption with AES and adding in- tegrity protection. As ESL is placed on the top of the standard controller interface, it can be integrated into any Bluetooth implementation. A prototype implementation of ESL is presented. The security processing is implemented in hardware for high performance. The design consumes fewer resources and has higher throughput (214 Mb/s) than the standard design. The programming interface supports straightforward application development.

Delay guarantee and bandwidth allocation for network services

Abstract: This paper presents a packet scheduling scheme for ensuring delay and bandwidth as a quality of service (QoS) requirement. For customers, rightful service is given while optimizing revenue of the network service provider. A gradient and fixed point type algorithms for updating the weights of a packet scheduler are derived from a revenue-based optimization problem. In the linear pricing scenario, algorithms are simple to implement. We compared algorithms with optimal brute-force method. Especially fixed point algorithm converges very fast to the optimal solution, typically in one iteration and about 40 operations, when number of classes is three. The weight updating procedures are independent on the assumption of the connections' statistical behavior, and therefore they are robust against erroneous estimates of statistics. Also, a call admission control (CAC) is implemented in context of our scenario.

Algorithmic optimization of H.264/AVC encoder

Abstract: Several platform independent optimizations for a baseline profile H.264/AVC encoder are described. The optimizations include adaptive diamond pattern based motion estimation, fast sub-pel motion vector refinement and heuristic intra prediction. In addition, loop unrolling, early out thresholds and adaptive inverse transforms are used. An experimental complexity analysis is presented studying effect of optimizations on the encoding frame rate on the AMD Athlon processor. Trade-offs in rate-distortion performance are also measured. Compared to a public reference encoder, speed-ups of 4-8 have been obtained with 0.6-0.8 dB loss in image quality. In practice, our software only H.264 encoder achieves an encoding rate of 86 QCIF frames/s that is well above real-time limits.

Flow-based fast handover performance analysis in mobile IPv6 for Linux environment

Abstract: In this paper we present a performance analysis of a recently proposed method flow-based fast handover method for mobile IPv6 (FFHMIPv6) in a real mobile IPv6 environment. The FFHMIPv6 uses the flow-state information and encapsulation to reduce the packet loss during the location update processes of mobile IPv6. In the experiments, the FFHMIPv6 handover is compared with the mobile IPv6 handover using the MIPL-based (mobile IPv6 for Linux) real network scenario. The effect of the distance of the nodes MN is communicating with, VoIP traffic and the processing delay caused by the FFHMIPv6 method are considered in the experiments. Also, some security aspects of the method have been considered. The FFHMIPv6 method has been found to be an efficient and a simple way to reduce the handover delay.

Bandwidth allocation, bit rate and pricing

Abstract: In this paper we present a packet scheduling method which guarantees bandwidth of the connection and optimizes revenue of the network service provider. A closed form formula for updating the adaptive weights of a packet scheduler is derived from a revenue-based optimization problem. The weight updating procedure is fast and independent on the assumption of the connections' statistical behavior. The features of the algorithm are simulated and analyzed with a call admission control (CAC) mechanism. We also show in context with the CAC procedure a mechanism for guaranteeing a specified mean bandwidth for different service classes.