We present the design and measurement results of millimeter-wave integrated circuits implemented in 65-nm baseline CMOS. Both active and passive test structures were measured. In addition, we present the design of an on-chip spiral balun and the transition from CPW to the balun and report transistor noise parameter measurement results at V-band. Finally, the design and measurement results of two amplifiers and a balanced resistive mixer are presented. The 40-GHz amplifier exhibits 14.3 dB of gain and the 1-dB output compression point is at +6-dBm power level using a 1.2 V supply with a compact chip area of 0.286 mm2. The 60-GHz amplifier achieves a measured noise figure of 5.6 dB at 60 GHz. The AM/AM and AM/PM results show a saturated output power of +7 dBm using a 1.2 V supply. In downconversion, the balanced resistive mixer achieves 12.5 dB of conversion loss and +5 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with -19 dBm of 1-dB output compression point.

Millimeter-Wave Integrated Circuits in 65-nm CMOS

In this paper, the design and analysis of CMOS multicascode configuration with noise reduction topology are proposed. Two low power and miniature low-noise amplifiers (LNAs) were designed and fabricated for demonstration. One with cascode device was designed at V -band in 65-nm process, and the other with triple-cascode structure was fabricated at Q -band in 0.13-? m technology. To minimize the noise figure and maximize the small-signal gain, inductors are designed and placed between transistors of the cascode and triple-cascode configurations. Based on this approach, the Q-band LNA has a gain of 14.3 dB and a noise figure of 3.8 dB at 38 GHz, with a power consumption of 28.8 mW. The V-band LNA presents a gain of 14.4 dB and a noise figure of 4.5 dB at 54.5 GHz, with a power consumption of 10 mW. The chip size of the V- and Q-band LNAs are 0.55 × 0.45 mm2 and 0.42 × 0.6 mm2, including all the testing pads. Compared with the conventional cascode LNAs, the proposed cascode LNA shows better noise figure and lower power consumption whereas the triple-cascode LNA features higher gain performance.

Millimeter-Wave Low Power and Miniature CMOS Multicascode Low-Noise Amplifiers with Noise Reduction Topology

This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (1P1) can be significantly increased to with the use of a high substrate resistance design. In contrast, of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13- CMOS designs can be used for state-of-the-art switches at 26-40 GHz.

$Ka$ -Band Low-Loss and High-Isolation Switch Design in 0.13- $\mu{\hbox {m}}$ CMOS

This paper presents a 77-GHz long-range automotive radar transceiver with the function of reducing mutual interference. The proposed frequency-hopping random chirp FMCW technique reconfigures the chirp sweep frequency and time every cycle to result in noise-like frequency response for mutual interference after the received signal is down-converted and demodulated. Thus, the false alarm rate can be reduced significantly. The transceiver IC is fully integrated in TSMC 1P9M 65-nm digital CMOS technology. The chip including pads occupies a silicon area of 1.03 mm × 0.94 mm. The transceiver consumes totally 275 mW of power, and the measured transmitting power and receiver noise figure are 6.4 dBm and 14.8 dB, respectively. To the authors' knowledge, this is the first integrated 77-GHz automotive radar transceiver with the feature of anti-interference.

A 77-GHz CMOS Automotive Radar Transceiver With Anti-Interference Function

In this paper, modified circuit topologies of a differential voltage-controlled oscillator (VCO) and a quadrature VCO (QVCO) in a standard bulk 90-nm CMOS process are presented for low dc power and low phase-noise applications. By utilizing current-reuse and transformer-feedback techniques, the proposed VCO and QVCO can be operated at reduced dc power consumption while maintaining extraordinary circuit performance in terms of low phase-noise and low amplitude/phase errors. The VCO circuit topology is investigated to obtain the design procedure. The VCO is further applied to the QVCO design with a bottom-series coupling technique. The coupling network between two differential VCOs and device size are properly designed based on our proposed design methodology to achieve low amplitude and phase errors. Moreover, the VCO and the QVCO are fully characterized with amplitude and phase errors via a four-port vector network analyzer. With a dc power of 3 mW, the VCO exhibits a frequency tuning range from 20.3 to 21.3 GHz, a phase noise of - 116.4 dBc/Hz at 1-MHz offset, a figure-of-merit (FOM) of -198 dBc/Hz, a phase error of 3.8° , and an amplitude error of 0.9 dB. With a dc power of 6 mW, the QVCO demonstrates a phase noise of -117.4 dBc/Hz, a FOM of -195.6 dBc/Hz, a phase error of 4° , and an amplitude error of 0.6 dB. The proposed VCO and QVCO can be compared with the previously reported state-of-the-art VCOs and QVCOs in silicon-based technologies.

$K$ -Band CMOS Differential and Quadrature Voltage-Controlled Oscillators for Low Phase-Noise and Low-Power Applications

A new topology for low power voltage controlled oscillators (VCOs) using a 0.18-mum CMOS foundry process is presented in this letter. From the measured results, the VCO exhibits a tuning range of 3% at 21.3 GHz. Using complementary topology, the core power consumption and the output power are 9.6 mW and -3 dBm, respectively. With the broadside coupled transformer, the VCO achieves a good phase noise of -106 dBc/Hz at 1 MHz offset and a compact chip size of 350 times 470 mum2. It is the first time that the broadside coupled transformer approach is applied to transformer coupled CMOS VCOs.

A 21 GHz Complementary Transformer Coupled CMOS VCO

A miniature Q-band low noise amplifier (LNA) using 0.13-/spl mu/m standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm/sup 2/. The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

A low phase-noise X-band push-push oscillator using proposed feedback topology is presented in this paper. The oscillator core was implemented in a 0.18-mum CMOS process. By using a power splitter and a delay path in the feedback loop connecting the output and current source of the oscillator, a part of the oscillator output power injects to the oscillator itself. With the proper phase delay in the feedback loop and high transconductance of the current source, a low phase-noise oscillator is achieved. The amplitude stability and phase stability are analyzed, the phenomena of the phase-noise reductions are derived, and the device-size selections of the oscillator are investigated. The time-variant function, impulse sensitivity function, is also adopted to analyze the phase-noise reductions of the second-harmonic self-injected push-push oscillator. These theories are verified by the experiments. This self-injected push-push oscillator achieves low phase noise of -120.1 dBc/Hz at 1-MHz offset from the 9.6-GHz carrier. The power consumption is 13.8 mW from a 1.0-V supply voltage. The figure-of-merit of the oscillator is -188.3 dBc/Hz. It is also the first attempt to analyze the second-harmonic self-injected push-push oscillator

Phase-Noise Reduction of $X$ -Band Push–Push Oscillator With Second-Harmonic Self-Injection Techniques

A downconversion double-balanced oscillator mixer using 0.18-mum CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A 6-stage travelling wave amplifier (TWA) implemented in a bulk 90nm CMOS technology is presented. By utilizing gate-line capacitive division and low-loss coplanar waveguides, the fabricated TWA exhibits 7.4dB gain with a 3dB bandwidth of 80GHz while maintaining input and output return losses better than 8dB from dc to 100GHz. A GBW of 190GHz is achieved.

To-Po Wang

Papers

A 21 GHz Complementary Transformer Coupled CMOS VCO

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

Phase-Noise Reduction of $X$ -Band Push–Push Oscillator With Second-Harmonic Self-Injection Techniques

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

An 80GHz travelling-wave amplifier in a 90nm CMOS technology