This paper describes the design and measurement of a wideband (W-band) passive radiometer chip developed in a standard 0.12-?m SiGe BiCMOS technology (IBM8HP, ft /fmax = 200/265 GHz). Design equations, simulations, and measurements are presented for a 94-GHz square-law detector and wideband low noise amplifier, and an 80-110-GHz single-pole double-throw switch. A total-power radiometer is presented, which can achieve a temperature resolution of ? 0.69 K (30-ms integration time) with periodic calibration or chopping above 10 kHz. A switched Dicke radiometer chip is also presented, which addresses the 1/f noise of the total-power radiometer, and can achieve a temperature resolution of 0.83 K with a 30-ms integration time. This performance is comparable to current III-V imaging modules, and demonstrates, to our knowledge, the first implementation of a SiGe or CMOS W -band radiometer on a single chip.

Design and Characterization of $W$ -Band SiGe RFICs for Passive Millimeter-Wave Imaging

This paper presents the comprehensive considerations of CMOS transmit/receive (T/R) switch design towards ultra-wideband and over 15-GHz frequencies. Techniques for minimizing parasitics and increasing linearity are discussed. A customized transistor layout is proposed for T/R switch design and its effects on insertion loss and isolation are studied. The analysis shows that a series-only architecture using the customized transistor layout achieves better insertion loss and reasonable isolation. A double-well body-floating technique is proposed and its effects are discussed. A differential switch architecture without shunt arms is designed and verified by experimental results. Fabricated in 0.13-mum triple-well CMOS, the T/R switch exhibits less than 2 dB insertion loss and higher than 21 dB isolation up to 20 GHz. With resistive body floating and differential architecture, the high linearity is of ultra-wideband characteristic, more than 30-dBm power 1-dB compression point (P1dB) is obtained up to 20 GHz in only 0.03 mm2 active die area.

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CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency

A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18- $\mu{\hbox {m}}$ CMOS T/R Switch

A fully integrated single-pole-double-throw transmit/receive switch has been designed and fabricated in standard bulk 90-nm complementary metal-oxide semiconductor (CMOS) technology. Traveling wave concept was used to minimize the insertion loss at higher frequency and widen the operating bandwidth. The switch exhibits a measured insertion loss of 2.7 -dB, an input 1-dB compression point (input P1 dB) of 15 dBm, and a 29-dB isolation at the center frequency of 77 GHz. The total chip size is only 0.57 times 0.42 mm 2 including all testing pads. To our knowledge, this is the first CMOS switch demonstrated beyond 50 GHz, and the performances rival those monolithic microwave integrated circuit switches using standard GaAs PHEMTs

A 50 to 94-GHz CMOS SPDT Switch Using Traveling-Wave Concept

This paper presents a fully integrated CMOS 60-GHz transceiver chipset for short-range and high-speed wireless communication. The target application of the short-range communication is less than 5-cm communication distance and more than 2-Gb/s throughput for file transfer. In order to achieve file transfer, physical (PHY) layers with error packet correction and media access control (MAC) layer with frame-exchanging function are implemented. The MAC is designed to have a high-efficiency feature due to short interval DATA/Acknowledgement (ACK) frame exchange. It is realized by fast transmitter (TX)/receiver (RX) switching. A bonding wire-based in-package antenna is adopted using a standard BGA package without any off-chip 60-GHz components. The proposed chipset is composed of two chips, an RF chip with in-package antenna, and a baseband chip including PHY and MAC layer. The fabricated chipset achieves 2.62-Gb/s PHY data rate, 2.07-Gb/s MAC throughput, and energy consumption of 651 pJ/bit in 3-cm distance.

A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication

A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

A downconversion double-balanced oscillator mixer using 0.18-mum CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A downconversion double-balanced oscillator mixer using 0.18- m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscil- lators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers. Index Terms—Oscillator mixer, self-oscillating mixer (SOM), voltage-controlled oscillator (VCO).

A Low-Power Oscillator Mixer in

A wide tuning range and low noise CMOS quadrature voltage-controlled oscillator (QVCO) using 0.18-mum 1P6M standard CMOS process is proposed in this paper. The VCO is realized employing switchable capacitors, so as to work in dual band and increase operation frequency. Moreover, the dual band operation could decrease the tuning sensitivity in each band and hence lower the phase noise. The VCO operates from 5.14 to 6.3 GHz with more than 20% tuning range. The measured phase noise at 1-MHz offset is -120.2 dBc/Hz at 5.5 GHz with VCO cores drawing total current of 8 mA at 1.8 V supply and the output power is about 1.5 dBm

Ying-Tang Chang

Papers

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A Low-Power Oscillator Mixer in

A Wide-band Low Noise Quadrature CMOS VCO