This paper presents a novel approach to design a digitally programmable low pass filter (LPF) and variable gain amplifier (VGA) intended for a software-defined radio (SDR) front-end. These flexible analog circuits are driven by a network-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by flexibility in analog design. A silicon prototype is realized in 0.13-μm CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive integrated noise level between 85 μVrms and 163 μVrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconfigurable power/bandwidth.

Flexible baseband analog circuits for software-defined radio front-ends

A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of $19.8\cdot 10^{-3}\ \text{mm}^{2}$ and is powered from 0.7 V with a standby current consumption of around 36 $\mu\text{A}$ . DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.

0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Fractional-order filters based on low-voltage DDCCs

In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from $V_{\mathbf {DD}}$ ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.

A Compact 0.3-V Class AB Bulk-Driven OTA

A new solution for a low-voltage bulk-driven CMOS operational amplifier is presented in this study. The amplifier is designed using 50 nm process parameters and optimised for 0.5 V supply voltage. The circuit consumes 100 μW, performing 74 dB open-loop gain, 59 nV/Hz1/2 input referred noise at 1 MHz and 4.8 MHz gain bandwidth product (GBP) for 20 pF load capacitance.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2012.0372

0.5-V bulk-driven CMOS operational amplifier

A new solution for an ultra-low-voltage, ultra-low-power operational transconductance amplifier (OTA) is presented in the paper. The design exploits a three-stage structure with a Reversed Miller Compensation Scheme, where the input stage is based on a non-tailed bulk-driven differential pair. Optimization of the structure for very low supply voltage is discussed. The resulting amplifier outperforms other ultra-low-voltage OTAs in terms of a DC voltage gain and power efficiency, expressed by standard figures of merit. Experimental verification using a $0.18~\mu \text{m}$ CMOS technology, with supply voltage of 0.3-V, showed a dissipation power of 13 nW, a DC voltage gain of 98 dB, a gain-bandwidth product of 3.1 kHz and an average slew-rate of 9.1 V/ms at 30 pF load capacitance. The experimental results agree well with simulations.

/pdf/a-0-3-v-98-db-rail-to-rail-ota-in-0-18-mu-m-cmos-53f3477wsp.pdf

A 0.3-V 98-dB Rail-to-Rail OTA in $0.18~\mu$ m CMOS

A new silicon realization of an ultra-low-voltage and ultra-low-power differential-difference amplifier (DDA) is presented in this paper The circuit combines the idea of non-tailed bulk-driven differential pairs with a partial positive feedback used for voltage gain boosting The DDA operates from $V_{\mathbf {DD}}$ ranging from 03 to 05 V For a 03-V version, the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 185 kHz, PSRR of 57 dB and the average slew-rate of 155 V/ms at 20 pF load capacitance, while consuming only 22 nW of power An instrumentation amplifier based on the proposed DDA showed the THD of 05 % for $V_{\mathbf {in}}=50$ mV $_{\mathbf {pp}}$ , and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V The circuit has been fabricated in a standard n-well $018~\mu \text{m}$ CMOS process from TSMC Chip test results agree with simulations A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions

Tomasz Kulej

Papers

0.5-V bulk-driven CMOS operational amplifier

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

A Compact 0.3-V Class AB Bulk-Driven OTA

A 0.3-V 98-dB Rail-to-Rail OTA in $0.18~\mu$ m CMOS

Design and Implementation of a 0.3-V Differential Difference Amplifier