Showing papers by "Veena Misra published in 2002"

Capacitance and conductance characterization of ferrocene-containing self-assembled monolayers on silicon surfaces for memory applications

Abstract: Self-assembled monolayers of 4-ferrocenylbenzyl alcohol attached to silicon provided the basis for electrolyte-molecule-silicon capacitors. Characterization by conventional capacitance and conductance techniques showed very high capacitance and conductance peaks near ∼0.6 V associated with charging and discharging of electrons into and from discrete levels in the monolayer owing to the presence of the redox-active ferrocenes. The reversible charge trapping of these molecules suggest their potential application in memory devices. Due to the molecular scalability and low-power operation, molecular-silicon hybrid devices may be strong candidates for next-generation electronic devices.

Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS

Abstract: In this letter, low resistivity Ru and Ru-Ta alloy films, deposited via reactive sputtering, were evaluated as gate electrodes for p- and n-MOSFET devices, respectively. MOSFETs fabricated via a conventional process flow indicated that the work functions of Ru and Ru-Ta alloys were compatible with p- and n-MOSFET devices, respectively. Both of the metal gated devices eliminated gate depletion effects. Good MOSFET characteristics, such as I/sub DS/-V/sub GS/ and mobility, were obtained for both Ru-gated PMOSFETs and Ru-Ta gated NMOSFETs.

Issues in High-ĸ Gate Stack Interfaces

Abstract: We address current challenges in the fundamental understanding of physical and chemical processes that occur in the fabrication of the transistor gate stack structure. Critical areas include (1) the interface between bulk silicon and high-dielectric-constant (high-ĸ) insulators, (2) the interface between high-ĸ insulators and advanced gate electrodes, and (3) the internal interfaces that form within dielectric stacks with nonuniform material and structure compositions. We approach this topic from a fundamental understanding of bonding and electronic structure at the interfaces, and of film-growth kinetics in comparison with thermodynamics predictions. Implications for the dielectric/electrode interface with metallic gates and issues with integration will also be presented.

Method and system for molecular charge storage field effect transistor

Abstract: A method and/or system and/or apparatus for a molecular-based FET device (an m-FET) uses charge storing molecules (120) between a gate (110) and channel (105) of an FET-type transistor. Further embodiments describe fabrication methods for using combinations of standard practices in lithography and synthetic chemistry and novel elements.

Methods of forming nano-scale electronic and optoelectronic devices using non-photolithographically defined nano-channel templates

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film The substrate insulating layer is then selectively etched to define a second array of nano-channels therein This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template An array of semiconductor nano-pillars is then formed in the second array of nano-channels The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer

Methods of forming nano-scale electronic and optoelectronic devices using non-photolithographically defined nano-channel templates and devices formed thereby

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.

Tunable work function dual metal gate technology for bulk and non-bulk CMOS

Abstract: This paper describes a metal gate process, which provides tunable work function values and ease of integration for dual metal gate process flow Vertical stacks of Ru and Ta layers were subjected to high temperature anneals to promote intermixing which resulted in /spl phi//sub m/ tuning It was found that Ru/Ta stacks provided up to 04 eV reduction in /spl phi//sub m/ compared to Ru To increase this change, stacks of Ru/sub 50/Ta/sub 50//Ru were also evaluated and nearly a 08 eV change in /spl phi//sub m/ was observed between Ru/sub 50/Ta/sub 50//Ru and Ru/sub 50/Ta/sub 50/ electrodes

Electrical characteristics of TaSixNy/SiO2/Si structures by Fowler–Nordheim current analysis

Abstract: In this letter, the Fowler–Nordheim tunneling in TaSixNy/SiO2/p-Si structures has been analyzed. The effective barrier height at the metal–oxide interface was extracted by Fowler–Nordheim current analysis. The barrier height was found to increase with increased annealing temperature. The barrier height was correlated with the extracted work function from capacitance–voltage analysis. This indicated that the work function of TaSixNy films changes under high temperature annealing from 4.2∼4.3 eV after 400 °C anneals to ∼4.8 eV after 900 °C anneals. We believe that the mechanism that causes the work function to increase is the formation of a Ta-disilicide layer at the interface between the electrode and the dielectric.

High/low work function metal alloys for integrated circuit electrodes

Abstract: Integrated circuit electrodes include an alloy of a first metal and a second metal having lower work function than the first metal. The second metal also may have higher oxygen affinity than the first metal. The first metal may be Ru, Ir, Os, Re and alloys thereof, and the second metal may be Ta, Nb, Al, Hf, Zr, La and alloys thereof. Both NMOS and the PMOS devices can include gate electrodes of an alloy of the first metal and the second metal having lower work function than the first metal. The PMOS gate electrode may have a higher percentage of the first metal relative to the second metal than the NMOS gate electrode. Thus, a common material system may be used for gate electrodes for both NMOS and PMOS devices.

High/low work function metal alloys for integrated circuit electrodes and methods of fabricating same

Abstract: Integrated circuit electrodes include an alloy of a first metal and a second metal having lower work function than the first metal The second metal also may have higher oxygen affinity than the first metal The first metal may be Ru, Ir, Os, Re and alloys thereof, and the second metal may be Ta, Nb, Al, Hf, Zr, La and alloys thereof Both NMOS and the PMOS devices can include gate electrodes of an alloy of the first metal and the second metal having lower work function than the first metal The PMOS gate electrode may have a higher percentage of the first metal relative to the second metal than the NMOS gate electrode Thus, a common material system may be used for gate electrodes for both NMOS and PMOS devices

The Effects of Nitrogen on Electrical and Structural Properties in TaSixNy/SiO2/p-Si MOS Capacitors

Abstract: In this work, we report the effects of nitrogen on electrical and structural properties in TaSixNy /SiO2/p-Si MOS capacitors. TaSixNy films with various compositions were deposited by reactive sputtering of TaSi2 or by co-sputtering of Ta and Si targets in argon and nitrogen ambient. TaSixNy films were characterized by Rutherford backscattering spectroscopy and Auger electron spectroscopy. It was found that the workfunction of TaSixNy (Si>Ta) with varying N contents ranges from 4.2 to 4.3 eV. Cross-sectional transmission electron microscopy shows no indication of interfacial reaction or crystallization in TaSixNy on SiO2, resulting in no significant increase of leakage current in the capacitor during annealing. It is believed that nitrogen retards reaction rates and improves the chemical-thermal stability of the gate-dielectric interface and oxygen diffusion barrier properties.