V
Venkata Rajesh Pamula
Researcher at University of Washington
Publications - 21
Citations - 212
Venkata Rajesh Pamula is an academic researcher from University of Washington. The author has contributed to research in topics: Signal & Biosignal. The author has an hindex of 5, co-authored 21 publications receiving 136 citations. Previous affiliations of Venkata Rajesh Pamula include Katholieke Universiteit Leuven & IMEC.
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Journal ArticleDOI
A 172 $\mu$W Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data
Venkata Rajesh Pamula,Jose Manuel Valero-Sarmiento,Long Yan,Alper Bozkurt,Chris Van Hoof,Nick Van Helleputte,Refet Firat Yazicioglu,Marian Verhelst +7 more
TL;DR: A compressive sampling (CS) photoplethysmographic (PPG) readout with embedded feature extraction to estimate heart rate (HR) directly from compressively sampled data is presented.
Journal ArticleDOI
A 680 nA ECG Acquisition IC for Leadless Pacemaker Applications
Long Yan,Pieter Harpe,Venkata Rajesh Pamula,Masato Osawa,Harada Yasunari,Kosei Tamiya,Chris Van Hoof,Refet Firat Yazicioglu +7 more
TL;DR: A sub- μW ECG acquisition IC is presented for a single-chamber leadless pacemaker applications that integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor.
Journal ArticleDOI
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS
John P. Uehlin,William Anthony Smith,Venkata Rajesh Pamula,Eric Pepin,Steve I. Perlmutter,Visvesh S. Sathe,Jacques C. Rudell +6 more
TL;DR: A prototype BBCI application-specified integrated circuit (ASIC) consisting of a 64-channel time-multiplexed recording front-end, an area-optimized four-channel high-voltage compliant stimulator, and electronics to support the concurrent multi-channel stimulus artifact cancellation is presented.
Proceedings ArticleDOI
14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
TL;DR: This work has shown that voltage domains continue to shrink in size, thus mandating a faster LDO response to compensate for reduced available decoupling capacitance (decap), and design margins to ensure stability across worst-case PVT conditions further degrade transient response.
Journal ArticleDOI
A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction
TL;DR: The proposed architecture presents a balanced approach to TRNG design, relying on a simpler, noncryptographic quality physical random number generator (RNG) combined with energy-efficient integrated post-processing to de-correlate and de-bias the bitstream.