V
Vincenzo Rana
Researcher at Polytechnic University of Milan
Publications - 69
Citations - 757
Vincenzo Rana is an academic researcher from Polytechnic University of Milan. The author has contributed to research in topics: Control reconfiguration & Reconfigurable computing. The author has an hindex of 15, co-authored 68 publications receiving 714 citations. Previous affiliations of Vincenzo Rana include École Normale Supérieure & École Polytechnique Fédérale de Lausanne.
Papers
More filters
Proceedings ArticleDOI
BlueSentinel: a first approach using iBeacon for an energy efficient occupancy detection system
TL;DR: This work presents BLUE-SENTINEL, an accurate and power efficient method to identify the occupants of each room of a smart building using mobile devices as source of information by exploiting iBeacon, a very recent low-power technology proposed by Apple.
Journal ArticleDOI
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
TL;DR: A design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC is presented and is actually able to extract similarities among the applications, as it achieves an average improvement in terms of reconfiguration latency with respect to a communication-oriented approach.
Proceedings ArticleDOI
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
Vincenzo Rana,Marco D. Santambrogio,Donatella Sciuto,Boris Kettelhoit,Markus Koester,Mario Porrmann,Ulrich Rückert +6 more
TL;DR: This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor that is referred to as a multi-FPGA clustered architecture (MFCA), which can be partially and dynamically reconfigured to integrate user-defined IP-cores into the system at run-time.
Book ChapterDOI
A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication
Vincenzo Rana,David Atienza,David Atienza,Marco D. Santambrogio,Donatella Sciuto,Giovanni De Micheli +5 more
TL;DR: Network-on-Chip has emerged as a very promising paradigm for designing scalable communication architecture for Systems- on-Chips (SoCs), but NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications.
Proceedings ArticleDOI
Dynamic Reconfigurability in Embedded System Design
TL;DR: The area of reconfigurable embedded systems is described presenting both architectural and methodological aspects trying to point out common features and needs, and an overview of the models of the reconfigured architectures, and of the design methodologies was presented.