This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems.

MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

Preparing the books to read every day is enjoyable for many people. However, there are still many people who also don't like reading. This is a problem. But, when you can support others to start reading, it will be better. One of the books that can be recommended for new readers is computer aided analysis of electronic circuits algorithms and computational techniques. This book is not kind of difficult book to read. It can be read and understand by the new readers.

Computer-aided analysis of electronic circuits: Algorithms and computational techniques

The eXtreme Processing Platform (XPPTM) is a new runtime-reconfigurable data processing architecture. It is based on a hierarchical array of coarsegrain, adaptive computing elements, and a packet-oriented communication network. The strength of the XPPTM technology originates from the combination of array processing with unique, powerful run-time reconfiguration mechanisms. Parts of the array can be configured rapidly in parallel while neighboring computing elements are processing data. Reconfiguration is triggered externally or even by special event signals originating within the array, enabling self-reconfiguring designs. The XPPTM architecture is designed to support different types of parallelism: pipelining, instruction level, data flow, and task level parallelism. Therefore this technology is well suited for applications in multimedia, telecommunications, simulation, signal processing (DSP), graphics, and similar stream-based application domains. The anticipated peak performance of the first commercial device running at 150 MHz is estimated to be 57.6 GigaOps/sec, with a peak I/O bandwidth of several GByte/sec. Simulated applications achieve up to 43.5 GigaOps/sec (32-bit fixed point).

PACT XPP—A Self-Reconfigurable Data Processing Architecture

[기술해설]암호법(Cryptography)

In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)

In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor. Next, we present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 μm, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.

Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor

Cloud applications are increasingly playing a crucial role in big data analytics. New use cases such as autonomous cars and edge computing call for novel approaches mixing heterogeneous computing and machine learning. These applications typically process petabyte-scale datasets, therefore, requiring low-power and scalable storage providing low-latency and high-throughput data access. While data centers have been focusing on migrating from legacy HDDs and SATA SSDs by deploying high-throughput and low-latency NVMe SSDs, the data bottlenecks appear as capacity scales. One approach to tackle this problem is to enable processing to happen within the storage device -in-storage processing (ISP)- eliminating the need to move the data. In this paper, we investigated the deployment of storage units with embedded low-power application processors along with FPGA-based reconfigurable hardware accelerators to address both performance and energy efficiency. To this purpose, we developed a high-capacity solid-state drive (SSD) named Catalina equipped with a quad-core ARM A53 processor running a Linux operating system along with a highly efficient FPGA accelerator for running applications in-place. We evaluated our proposed approach on a case study application for a similarity search library called Faiss.

Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics

In this paper we present a new approach to the test of multi-port RAMS. A new fault model that takes into account complex couplings resulting from simultaneous access of memory cells is used in order to ensure a very high fault coverage. A new algorithm for the test of dual-port memories is here detailed. This algorithm achieves qn) complexity thanks to the use of some topological restrictions. We also present a new BlST scheme, based on programmable schematic generators, that allows great flexibility for ASIC design. I - INTRODUCTION Multi-port RAMS are widely used as embedded memories in telecommunication ASlCs and also in multi-processor systems. These special RAM chips are provided by IC vendors as well as multi-port RAM generators that are already available in some ASIC vendors libraries. The testing of these memories is getting more important since they are often embedded in VLSl and ULSl circuits (RAT 901. Efficient algorithms for the test of multi-port RAMS can thus be used in two ways : ASIC libraries providing test algorithms and ASIC libraries providing BIST circuit generators as an option for the multi-port RAM generator. Multi-port RAMS differ from single port RAMS by the possibility of accessing more than one cell at a time. Various authors have studied the fault modeling of single port RAMS as well as test algorithms for the detection of such faults. Coupling faults are a widely used model for the testing of single port RAMS (SUK 811 (THA 781. Recent work on multi-port RAM testing use the same coupling fault models (RAP 88) (NAD 90) or Induction Fault Analysis extracted faults (SAS 901 (which do not take couplings into account). In (CASSl), we have shown that the above fault model is not sufficient in order to test multi-port RAMS. Thus, we have introduced the complex coupling faults. In section II we briefly review the concept of complex coupling. In this paper, we detail an algorithm based on a topdogical approach that results in an O(n) complexity test algorithm with a very high fault coverage. Conceming the implementation of the algorithm and in order to be compatible with the high flexibility provided by ASIC libraries RAM generators, we have developed a totally parameterizable BlST circuit. The development is done using GDP tools and the THOMSON Composants Militaires et Spatiaux (TMS) CSAM ASIC compiled function library.

Built-In Self-Test for Multi-Port RAMs.

The solution described here is a method to provide consistent performance in a storage device. A performance manager module is implemented to measure the time interval in which a command takes to be completed. In case the time interval is longer than a certain threshold, the difference is annotated and used on the consecutive commands within a programmable time window. This time window can be a regular time interval e.g. every second. In case the time interval is shorter than a threshold, the control module delays sending the command completion to the host until the threshold value is reached. The delay is adjusted based on the credit annotation due to commands that took longer than the time interval to be completed in order to compensate for commands that took longer than the threshold to complete, during a certain time window.

System and method for providing consistent, reliable, and predictable performance in a storage device

This work proposes a new BIST scheme for 2nd order Butterworth, Chebyshev and Bessel filter approximations, using the transient analysis of simple input test vectors. A functional approach for fault modeling in 2nd order filters is presented and the transient response method is used for fault detection. The approach considers the filter as a 2nd order dynamic system where /spl omega/c and Qp deviations are faults to be detected. The peak time is the observed parameter that is evaluated in order to verify the filter correctness. The obtained results are very promising since all of /spl omega/c and Qp deviations as well as 100% of passive components are detected for this BIST scheme.

Vladimir Alves

Papers

Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor

Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics

Built-In Self-Test for Multi-Port RAMs.

System and method for providing consistent, reliable, and predictable performance in a storage device

Fault detection methodology and BIST method for 2nd order Butterworth, Chebyshev and Bessel filter approximations