Journal ArticleDOI
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Ming-Hau Lee,H. Singh,Guangming Lu,Nader Bagherzadeh,Fadi J. Kurdahi,Eliseu M. Chaves Filho,Vladimir Alves +6 more
- Vol. 24, Iss: 2, pp 147-164
TLDR
The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.Abstract:
In this paper, we describe the implementation of MorphoSys, a reconfigurable processing system targeted at data-parallel and computation-intensive applications. The MorphoSys architecture consists of a reconfigurable component (an array of reconfigurable cells) combined with a RISC control processor and a high bandwidth memory interface. We briefly discuss the system-level model, array architecture, and control processor. Next, we present the detailed design implementation and the various aspects of physical layout of different sub-blocks of MorphoSys. The physical layout was constrained for 100 MHz operation, with low power consumption, and was implemented using 0.35 μm, four metal layer CMOS (3.3 Volts) technology. We provide simulation results for the MorphoSys architecture (based on VHDL model) for some typical data-parallel applications (video compression and automatic target recognition). The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.read more
Citations
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Journal ArticleDOI
PACT XPP—A Self-Reconfigurable Data Processing Architecture
TL;DR: The eXtreme Processing Platform (XPPTM) is a new runtime-reconfigurable data processing architecture based on a hierarchical array of coarsegrain, adaptive computing elements, and a packet-oriented communication network that is well suited for applications in multimedia, telecommunications, simulation, signal processing, graphics, and similar stream-based application domains.
Patent
Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like)
Martin Vorbach,Robert Münch +1 more
TL;DR: In this paper, the first result data may be obtained using a plurality of configurable coarse-granular elements, and the first results may be subsequently processed using the plurality of configured granular elements.
Patent
Data processing device and method
Martin Vorbach,Alexander Thomas +1 more
TL;DR: In this paper, a data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses or communication lines operated at a second clock rate is described.
Patent
Data processing method and device
TL;DR: In this article, the first result data may be obtained using a plurality of configurable coarse-granular elements, and the first results may be subsequently processed using the plurality of configured granular elements.
Proceedings ArticleDOI
EPIMap: using epimorphism to map applications on CGRAs
TL;DR: Experimental results on 14 important kernels extracted from well known benchmark programs show that using EPIMap can improve the performance of the kernels on CGRA by more than 2.8X on average, as compared to one of the best existing mapping algorithm, EMS.
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