E
Eliseu M. Chaves Filho
Researcher at Federal University of Rio de Janeiro
Publications - 9
Citations - 445
Eliseu M. Chaves Filho is an academic researcher from Federal University of Rio de Janeiro. The author has contributed to research in topics: Reduced instruction set computing & Reconfigurable computing. The author has an hindex of 6, co-authored 9 publications receiving 439 citations.
Papers
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Journal ArticleDOI
Design and Implementation of the MorphoSys Reconfigurable ComputingProcessor
Ming-Hau Lee,H. Singh,Guangming Lu,Nader Bagherzadeh,Fadi J. Kurdahi,Eliseu M. Chaves Filho,Vladimir Alves +6 more
TL;DR: The results indicate that the MorphoSys system can achieve significantly better performance for most of these applications in comparison with other systems and processors.
Book ChapterDOI
The MorphoSys Parallel Reconfigurable System
TL;DR: This paper introduces MorphoSys, a parallel system-on-chip which combines a RISC processor with an array of coarse-grain reconfigurable cells which shows significant performance enhancements for different classes of applications, as compared to conventional architectures.
Proceedings ArticleDOI
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications
H. Singh,Guangming Lu,Eliseu M. Chaves Filho,Rafael Maestre,Ming-Hau Lee,Fadi J. Kurdahi,Nader Bagherzadeh +6 more
TL;DR: A case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications.
Proceedings ArticleDOI
The MorphoSys dynamically reconfigurable system-on-chip
Guangming Lu,H. Singh,Ming-Hau Lee,Nader Bagherzadeh,Fadi J. Kurdahi,Eliseu M. Chaves Filho,V. Castro-Alves +6 more
TL;DR: Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors.
Proceedings ArticleDOI
MorphoSys: a reconfigurable architecture for multimedia applications
TL;DR: The MorphoSys reconfigurable system, which combines a reconfigured array of processor cells with a RISC processor core and a high bandwidth memory interface unit, is described and its efficacy is demonstrated through simulation of video compression and target-recognition applications.