In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

Recent Advances and Trends in Advanced Packaging

A new SX-Aurora TSUBASA vector supercomputer has been released, and it features a new system architecture and a new execution model to achieve high sustained performance, especially for memory-intensive applications. In SX-Aurora TSUBASA, the vector host (VH) of a standard x86 Linux node is attached to the vector engine (VE) of the newly developed vector processor. An application is executed on the VE, and only system calls are offloaded to the VH. This new execution model can avoid redundant data transfers between the VH and VE that can easily become a bottleneck in the conventional execution model. This paper examines the potential of SX-Aurora TSUBASA. First, the basic performance is clarified by evaluating benchmark programs. Then, the effectiveness of the new execution model is examined by using a microbenchmark. Finally, the potential of SX-Aurora TSUBASA is clarified through evaluations of practical applications.

Performance evaluation of a vector supercomputer SX-aurora TSUBASA

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

As 4th industry revolution becomes realization, more sophisticated mobile sets and servers are demanded that, in turn, necessitates advanced package technologies. For mobile applications, Package on package (POP) and interposer POP have been widely used. When a laminate organic substrate is replaced by wafer level process, the electrical and thermal performances are greatly enhanced. However, a significant cost is added due to new wafer-level packaging equipment. For network systems and high-performance computing server applications perspective, a silicon interposer is increasingly adapted to integrate HBM (High-Bandwidth Memory) with various controller or logic devices. The merits of fine line and space design rule of silicon interposer cannot be found in any other package platforms. However, the silicon interposers suffer from costly TSVs and the lossy substrate which limits electrical performance. In this paper, three RDL based platforms (FO-PLP, FO-SIP and RDL Interposer) are introduced. An adequate platform can be chosen by considering package size (FO-PLP for mobile applications), thermal performance (FO-SIP for intelligent devices in near-future), competitive cost (RDL Interposer for servers as in consumer products). Nevertheless, RDL based platforms and 2.5D silicon interposer are not cannibalizing one another.

Advanced Fan-Out Package SI/PI/Thermal Performance Analysis of Novel RDL Packages

Chip-on-Wafer-on-Substrate with Si interposer (CoWoS-S) is a TSV-based multi-chip integration technology that is widely used in high performance computing (HPC) and artificial intelligence (AI) accelerator area due to its flexibility to accommodate multiple chips of SoC, chiplet, and 3D stacks such as high bandwidth memory (HBM). The interposer size increases steadily over the past few years, from one full reticle size (∼830 mm2) to two reticle size (∼1700 mm2). The growth of interposer size offers more integration power to accommodate more active silicon in a package to satisfy the HPC/AI needs. In this paper, we report the new 5th generation CoWoS-S (CoWoS-S5) based on a Si interposer as large as three full reticle size (∼2500 mm2) by a novel 2-way lithography stitching approach. This will accommodate a multiple of logic chips at a total area of 1200 mm2 (with chiplets) together with eight HBM stacks. Besides the dimensional increase of the Si interposer, new features are incorporated to further enhance the electrical and thermal performances of CoWoS-S5 compared with the previous CoWoS-S portfolio. These include an integrated deep trench capacitor (iCap) for enhanced power integrity, 5 layers of sub-micron Cu interconnect with reduced sheet resistance to satisfy high speed die to die interconnect, new TSV structure interposer for both return and insertion loss reduction, and a higher thermal conductivity thermal interface material (TIM) to achieve a lower thermal resistance. Component level reliability with excellent electrical and physical results are also discussed.

Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2

State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200mm2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.

W. H. Wei

Papers

Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology

Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2