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Convex Analysisの二,三の進展について

Praise for the Third Edition: "This is one of the best books available. Its excellent organizational structure allows quick reference to specific models and its clear presentation . . . solidifies the understanding of the concepts being presented."IIE Transactions on Operations EngineeringThoroughly revised and expanded to reflect the latest developments in the field, Fundamentals of Queueing Theory, Fourth Edition continues to present the basic statistical principles that are necessary to analyze the probabilistic nature of queues. Rather than presenting a narrow focus on the subject, this update illustrates the wide-reaching, fundamental concepts in queueing theory and its applications to diverse areas such as computer science, engineering, business, and operations research.This update takes a numerical approach to understanding and making probable estimations relating to queues, with a comprehensive outline of simple and more advanced queueing models. Newly featured topics of the Fourth Edition include:Retrial queuesApproximations for queueing networksNumerical inversion of transformsDetermining the appropriate number of servers to balance quality and cost of serviceEach chapter provides a self-contained presentation of key concepts and formulae, allowing readers to work with each section independently, while a summary table at the end of the book outlines the types of queues that have been discussed and their results. In addition, two new appendices have been added, discussing transforms and generating functions as well as the fundamentals of differential and difference equations. New examples are now included along with problems that incorporate QtsPlus software, which is freely available via the book's related Web site.With its accessible style and wealth of real-world examples, Fundamentals of Queueing Theory, Fourth Edition is an ideal book for courses on queueing theory at the upper-undergraduate and graduate levels. It is also a valuable resource for researchers and practitioners who analyze congestion in the fields of telecommunications, transportation, aviation, and management science.

Fundamentals of Queueing Theory

Computer and Robot Vision Vol. 1, by R.M. Haralick and Linda G. Shapiro, Addison-Wesley, 1992, ISBN 0-201-10887-1.

Computer and Robot Vision

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

A modular intelligent transportation system, comprising an environmentally protected enclosure, a system communications bus, a processor module, communicating with said bus, having a image data input and an audio input, the processor module analyzing the image data and/or audio input for data patterns represented therein, having at least one available option slot, a power supply, and a communication link for external communications, in which at least one available option slot can be occupied by a wireless local area network access point, having a communications path between said communications link and said wireless access point, or other modular components.

Modular intelligent transportation system

Noise characteristics of a single sensor camera in digital color image processing

Network-on-Chip (NoC) have become favorable for on-chip communication, especially with the ever rising number of communication partners in future manycore system-on-chip. NoCs that are based on mesh topologies with dimension-routing are well-established as they scale well with the increasing number of communication partners and allow efficient router design. To be able to serve application demands with efficiency, sophisticated features such as multicasting become an increasingly important factor in future NoC-based systems. The 2D-mesh/dimension-routing combination, however, suffers from performance degradation especially in the case of multicast communication as the network infrastructure is utilized suboptimally. Approaching this problem, we investigate the potential of network-coded Network-on-Chip (ncNoC) compared to classical 2D-mesh/dimension-routing NoCs. We adapt a high level evaluation method to compute the minimum hop count equivalent using network coding which enables us to compare network-coded and dimension-routed hop count cost. Within this environment we can demonstrate the full potential of network coding for both the butterfly and generalized multicast connection settings. We can show that network coding is never outperformed by dimension-routing in terms of required hop counts and, more important, identify multi-source scenarios with only a limited number of sinks per source to be the most advantageous connection settings for coded NoCs.

Evaluation of hop count advantages of network-coded 2D-mesh NoCs

The reduction of CMOS structures into the nanometer regime, as well as the high demand for low-power applications, animating to further reduce the supply voltages towards the threshold, results in an increased susceptibility of integrated circuits to soft errors. Hence, circuit reliability has become a major concern in today's VLSI design process. A new approach to further support these trends is to relax the reliability requirements of a circuit, while ensuring that the functionality of the circuit remains unaffected, or effects remain unnoticed by the user. To realize such an approach it is necessary to determine the probability of an error at the output of a circuit, given an error probability distribution at the circuits' elements. Purely software-based simulation approaches are unsuitable due to the large simulation times. Hardware-accelerated approaches exist, but lack the ability to inject errors based on probabilities, are slow or have a large area overhead. In this paper we propose a novel approach for FPGA-based, probabilistic, circuit fault simulation. The proposed system is a mainly hardware-based, which makes the simulation fast, but also keeps the hardware overhead on the FPGA low by exploiting FPGA specific features.

A resource-efficient probabilistic fault simulator

Intelligent, semi-autonomous prostheses take ad-vantage of combining autonomous functions and traditional myoelectric control. With the help of visual and environment sensors, intelligent prostheses achieve a level of autonomy which relieves the user from generating elaborate electromyographic (EMG) signals for grasp type and trajectory. To achieve the desired functionality, the semi-autonomous prosthesis must efficiently process the incoming environmental data at a high rate, with low power and high accuracy. In this paper, we propose Binary-LoRAX, a low-latency runtime adaptable classifier for the semi-autonomous grasping task of prosthetic hands. We offload the classification task to an efficient binary neural network accelerator which performs high-throughput XNOR operations on digital signal processing (DSP) blocks. To tailor the classifier’s performance to the current application scenario, we propose a frequency scaling approach which dynamically switches between two modes of operation, high-performance and power-saving. At high-performance, classifications are performed with a low latency of 0.45ms, high-throughput of 4999 FPS and power consumption of ∼ 2.15 W. This enables functions such as object localization and batch classification. Switching to power-saving mode, a latency of 80 ms is maintained, with up to 19% improved classifier battery-life. Our prototypes achieve a high accuracy of up to 99.82% on a 25 class problem from the YCB graspable object dataset.

Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands

Recently, software performance estimation based on source cod instrumentation shows promising results in the literature. It achieves significant speedup without compro mising accuracy, compared with cycle-accurate simulations. However, much work still remains to be done to make thi s technique flexible and accurate enough to estimate arbitrary applications on complex processors. To the best o f our knowledge, we are the first to propose ways to tackle microarchitecture-related issues in the source cod instrumentation approach. We perform static instruction scheduling for superscalar architectures at instrumentat io time and propose combined execution of instrumented code and processor component simulators to model runtime in teractions between software and microarchitecture. We have developed a new framework, SciSim, to provide a common infrastructure for the proposed approa ch. It is designed to be easily extendable and retargetable to di fferent instruction set architectures and processors. Experiments with standard benchmarks are presented to vali date our approach.

Walter Stechele

Papers

Noise characteristics of a single sensor camera in digital color image processing

Evaluation of hop count advantages of network-coded 2D-mesh NoCs

A resource-efficient probabilistic fault simulator

Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands

Fast and Accurate Software Performance Estimation during High-Level Embedded System Design