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Walter Stechele

Researcher at Technische Universität München

Publications -  200
Citations -  1981

Walter Stechele is an academic researcher from Technische Universität München. The author has contributed to research in topics: Control reconfiguration & Field-programmable gate array. The author has an hindex of 21, co-authored 189 publications receiving 1746 citations. Previous affiliations of Walter Stechele include Ludwig Maximilian University of Munich.

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A reasoning approach to enable abductive semantic explanation upon collected observations for forensic visual surveillance

TL;DR: A layered reasoning pipeline that combines abductive logic programming together with backward and forward chaining based deductive Logic programming is proposed that will enable automatic generation of probable semantic hypotheses for a given set of collected observations for forensic visual surveillance.
Proceedings ArticleDOI

Architectural Vulnerability Factor Estimation with Backwards Analysis

TL;DR: This method considers all major masking effects in a single algorithm and delivers results in several levels of detail from average AVF through sensitivity waveforms, which could be used for reliability assessment and selective hardening of the circuit to reach a target failure rate.
Proceedings ArticleDOI

MPEG-7 binary format for XML data

TL;DR: Compared to the standard text compressor ZIP, or the XML-optimized tool XMill, the MPEG-7 binary format achieves a 2-5 times better compression of the document structure and provides additional functionalities that increase the flexibility and make it useful in broadcast applications and scenarios with limited bandwidth.
Proceedings ArticleDOI

AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms

TL;DR: An analytical co-design methodology, which enables two genetic algorithms to evaluate the fitness of design decisions on layer-wise quantization of a neural network and hardware (HW) resource allocation, and harness the speed and flexibility of analytical HW-modeling to enable parallel HW-CNN co- design.