/pdf/convex-analysisnoer-san-nojin-zhan-nituite-5dl2rbmoyr.pdf

Convex Analysisの二,三の進展について

Praise for the Third Edition: "This is one of the best books available. Its excellent organizational structure allows quick reference to specific models and its clear presentation . . . solidifies the understanding of the concepts being presented."IIE Transactions on Operations EngineeringThoroughly revised and expanded to reflect the latest developments in the field, Fundamentals of Queueing Theory, Fourth Edition continues to present the basic statistical principles that are necessary to analyze the probabilistic nature of queues. Rather than presenting a narrow focus on the subject, this update illustrates the wide-reaching, fundamental concepts in queueing theory and its applications to diverse areas such as computer science, engineering, business, and operations research.This update takes a numerical approach to understanding and making probable estimations relating to queues, with a comprehensive outline of simple and more advanced queueing models. Newly featured topics of the Fourth Edition include:Retrial queuesApproximations for queueing networksNumerical inversion of transformsDetermining the appropriate number of servers to balance quality and cost of serviceEach chapter provides a self-contained presentation of key concepts and formulae, allowing readers to work with each section independently, while a summary table at the end of the book outlines the types of queues that have been discussed and their results. In addition, two new appendices have been added, discussing transforms and generating functions as well as the fundamentals of differential and difference equations. New examples are now included along with problems that incorporate QtsPlus software, which is freely available via the book's related Web site.With its accessible style and wealth of real-world examples, Fundamentals of Queueing Theory, Fourth Edition is an ideal book for courses on queueing theory at the upper-undergraduate and graduate levels. It is also a valuable resource for researchers and practitioners who analyze congestion in the fields of telecommunications, transportation, aviation, and management science.

Fundamentals of Queueing Theory

Computer and Robot Vision Vol. 1, by R.M. Haralick and Linda G. Shapiro, Addison-Wesley, 1992, ISBN 0-201-10887-1.

Computer and Robot Vision

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[서평]「Computer Organization and Design, The Hardware/Software Interface」

A modular intelligent transportation system, comprising an environmentally protected enclosure, a system communications bus, a processor module, communicating with said bus, having a image data input and an audio input, the processor module analyzing the image data and/or audio input for data patterns represented therein, having at least one available option slot, a power supply, and a communication link for external communications, in which at least one available option slot can be occupied by a wireless local area network access point, having a communications path between said communications link and said wireless access point, or other modular components.

Modular intelligent transportation system

Egomotion compensation and moving objects detection algorithm on GPU.

Autonomic Systems on Chip provision VLSI systems with the capabilities of self-organization, self-healing and self-optimization, thereby allowing them to adapt to their environment and improve their functionality through run-time learning. This paper presents our current status of work on autonomic SoC architectures, beginning with a robust, self-correcting processor data path architecture and progressing to reinforcement machine learning techniques for self-optimization and self-organization at run time. An outlook of our future work and upcoming challenges in regard to autonomic systems on chip is then presented as a basis for discussion at the SORT workshop, and with the organic computing community in general.

Towards Scalability and Reliability of Autonomic Systems on Chip

As more deep learning algorithms enter safety-critical application domains, the importance of analyzing their resilience against hardware faults cannot be overstated. Most existing works focus on bit-flips in memory, fewer focus on compute errors, and almost none study the effect of hardware faults on adversarially trained convolutional neural networks (CNNs). In this work, we show that adversarially trained CNNs are more susceptible to failure due to hardware errors when compared to vanilla-trained models. We identify large differences in the quantization scaling factors of the CNNs which are resilient to hardware faults and those which are not. As adversarially trained CNNs learn robustness against input attack perturbations, their internal weight and activation distributions open a backdoor for injecting large magnitude hardware faults. We propose a simple weight decay remedy for adversarially trained models to maintain adversarial robustness and hardware resilience in the same CNN. We improve the fault resilience of an adversarially trained ResNet56 by 25% for large-scale bit-flip benchmarks on activation data while gaining slightly improved accuracy and adversarial robustness.

Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs

Concept and Design of an SNR-adaptive DRM+/FM Receiver using Dynamic Partial Reconfiguration (DPR) of FPGAs

Shutterless frame store charge-coupled devices (CCDs) are commonly used in ground-based solar observations, but the characteristical readout smear error of such devices hinders an application of frame store CCDs to autonomous missions. The combination of polarimetric modulation and image accumulation disables a correction of this error via software-based post-facto processing if in addition microvibrations occur during flight. This paper presents the first FPGA-based architecture for online smear correction of images from frame store CCDs, which allows for the usage of a certain frame store CCD camera on a balloon-borne solar observatory. First, we explore fast convolution-based algorithms with respect to their properties for an implementation. Afterwards, a hardware architecture is derived and implemented. Our results show that 400 frames of megapixel size can be corrected per second, maintaining an acceptable power consumption of less than 12 Watt. Finally, we discuss the circuit and show the degrees of freedom for further designs.

Walter Stechele

Papers

Egomotion compensation and moving objects detection algorithm on GPU.

Towards Scalability and Reliability of Autonomic Systems on Chip

Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs

Concept and Design of an SNR-adaptive DRM+/FM Receiver using Dynamic Partial Reconfiguration (DPR) of FPGAs

Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter