W
Walter Stechele
Researcher at Technische Universität München
Publications - 200
Citations - 1981
Walter Stechele is an academic researcher from Technische Universität München. The author has contributed to research in topics: Control reconfiguration & Field-programmable gate array. The author has an hindex of 21, co-authored 189 publications receiving 1746 citations. Previous affiliations of Walter Stechele include Ludwig Maximilian University of Munich.
Papers
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Proceedings ArticleDOI
VLSI architecture for variable block size motion estimation with luminance correction
Peter M. Kuhn,Walter Stechele +1 more
TL;DR: The architecture and application of a flexible 100 GOPS (giga operations per second) exhaustive search segment matching VLSI architecture to support evolving motion estimation algorithms as well as block matching algorithms of established video coding standards are described.
Proceedings ArticleDOI
Multithreaded virtual-memory-enabled reconfigurable hardware accelerators
TL;DR: A system layer is introduced that provides unified virtual memory, platform-agnostic interfacing, and multithreaded execution, for hardware accelerators running within the same OS process with user software, and achieves significant speedups over software with only limited overheads.
Proceedings ArticleDOI
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors
TL;DR: This reliable processor pipeline architecture resilient to multiple soft- and timing errors and probabilistic quantification of its performance overheads is presented, which is therefore much better than techniques based on flushing.
Journal ArticleDOI
Resource-awareness on heterogeneous MPSoCs for image processing
Johny Paul,Walter Stechele,Benjamin Oechslein,Christoph Erhardt,Jens Schedel,Daniel Lohmann,Wolfgang Schröder-Preikschat,Manfred Kröhnert,Tamim Asfour,Ericles Sousa,Vahid Lari,Frank Hannig,Jürgen Teich,Artjom Grudnitsky,Lars Bauer,Jorg Henkel +15 more
TL;DR: A case study demonstrates that a resource-aware programming model called Invasive Computing helps to improve the throughput and worst observed latency of the application program, by dynamically mapping applications to different types of PEs available on a heterogeneous MPSoC.
Proceedings ArticleDOI
OrthrusPE: runtime reconfigurable processing elements for binary neural networks
TL;DR: This paper exploits DSP48 blocks on off-the-shelf FPGAs to compute binary Hadamard products and fixed-point arithmetic, thereby utilizing the same hardware resource for two distinct, critical modes of operation.