W
Walter Stechele
Researcher at Technische Universität München
Publications - 200
Citations - 1981
Walter Stechele is an academic researcher from Technische Universität München. The author has contributed to research in topics: Control reconfiguration & Field-programmable gate array. The author has an hindex of 21, co-authored 189 publications receiving 1746 citations. Previous affiliations of Walter Stechele include Ludwig Maximilian University of Munich.
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Proceedings ArticleDOI
Adversarial Robust Model Compression using In-Train Pruning
Manoj Rohit Vemparala,Nael Fasfous,Alexander Frickenstein,Sreetama Sarkar,Qi Zhao,Sabine Kuhn,Lukas Frickenstein,Anmol Singh,Christian Unger,Naveen Shankar Nagaraja,Christian Wressnegger,Walter Stechele +11 more
TL;DR: The authors combine adversarial training and model pruning in a joint formulation of the fundamental learning objective during training to reduce the model size and robustness against adversarial attacks, achieving an 85 % reduction in parameters for ResNet20 on CIFAR-10 dataset.
Proceedings ArticleDOI
Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness
TL;DR: A novel power-driven logic synthesis methodology is employed which enables DSVS in addition to state-of-the-art optimization techniques, and DSVS generally further reduced the power consumption of combinational circuits by up to 16%, while GSVS actually led to higher power consumption in 50% of the test cases, compared with SSV optimization.
Book ChapterDOI
AutoVision - Reconfigurable Hardware Acceleration for Video-Based Driver Assistance
TL;DR: The aim of this project was to find out how to use fast dynamic partial reconfiguration to load and operate the right hardware accelerator engines in time (without loosing a single video frame), while removing unused engines in order to save precious chip area.
Proceedings ArticleDOI
Flexible low-power VLSI architecture for MPEG-4 motion estimation
TL;DR: The aim of the presented VLSI architecture was to gain high efficiency at low memory bandwidth requirements for the computationally demanding algorithms as well as the support of several motion estimation algorithmic features with less additional area overhead.
Book ChapterDOI
Applying ASoC to Multi-core Applications for Workload Management
Johannes Zeppenfeld,Abdelmajid Bouajila,Walter Stechele,Andreas Bernauer,Oliver Bringmann,Wolfgang Rosenstiel,Andreas Herkersdorf +6 more
TL;DR: In this article, the authors present the use of decentralised self-organisation concepts for the efficient dynamic parameterization of hardware components and the autonomic distribution of tasks in a symmetrical multi-core processor system.