Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TLDR
In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.Abstract:
MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologiesread more
Citations
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Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Patent
Semiconductor device, and manufacturing method thereof
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Book
FinFETs and Other Multi-Gate Transistors
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.
Journal ArticleDOI
Silicon Vertically Integrated Nanowire Field Effect Transistors
TL;DR: In this paper, the authors demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowires assembly processes.
Journal ArticleDOI
Frontiers of silicon-on-insulator
TL;DR: In this article, the authors discuss methods of forming silicon-on-insulator (SOI) wafers, their physical properties, and the latest improvements in controlling the structure parameters.
References
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Journal ArticleDOI
Scaling theory for double-gate SOI MOSFET's
TL;DR: In this paper, a scaling theory for double-gate SOI MOSFETs is presented, which gives guidance for device design that maintains a sub-threshold factor for a given gate length.
Proceedings ArticleDOI
A folded-channel MOSFET for deep-sub-tenth micron era
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,E. Anderson,Hideki Takeuchi,K. Asano,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +8 more
TL;DR: In this paper, a quasi-planar fold-channel transistor structure was proposed for the vertical double-gate SOI MOSFETs, which improved the short channel effect immunities.
Proceedings ArticleDOI
Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?
TL;DR: In this paper, Monte Carlo simulation is used to explore the characteristics of an n-channel MOSFET at the presently perceived limits of scaling, including a transconductance as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps.
Journal ArticleDOI
Impact of the vertical SOI 'DELTA' structure on planar device technology
TL;DR: In this paper, a fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented.
Journal ArticleDOI
Electrical properties of heavily doped polycrystalline silicon-germanium films
TL;DR: In this article, the electrical properties of polycrystalline silicon-germanium (poly-Si/sub 1/spl minus/x/Ge/sub x/) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented.