Atomically thin molybdenum disulfide (MoS2) is an ideal semiconductor material for field-effect transistors (FETs) with sub-10 nm channel lengths. The high effective mass and large bandgap of MoS2 minimize direct source–drain tunneling, while its atomically thin body maximizes the gate modulation efficiency in ultrashort-channel transistors. However, no experimental study to date has approached the sub-10 nm scale due to the multiple challenges related to nanofabrication at this length scale and the high contact resistance traditionally observed in MoS2 transistors. Here, using the semiconducting-to-metallic phase transition of MoS2, we demonstrate sub-10 nm channel-length transistor fabrication by directed self-assembly patterning of mono- and trilayer MoS2. This is done in a 7.5 nm half-pitch periodic chain of transistors where semiconducting (2H) MoS2 channel regions are seamlessly connected to metallic-phase (1T′) MoS2 access and contact regions. The resulting 7.5 nm channel-length MoS2 FET has a low ...

MoS2 Field-Effect Transistor with Sub-10 nm Channel Length

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications.

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III–V compound semiconductor transistors—from planar to nanowire structures

Low-dimensional semiconductor materials structures, where nanowires are needle-like one-dimensional examples, have developed into one of the most intensely studied fields of science and technology. The subarea described in this review is compound semiconductor nanowires, with the materials covered limited to III-V materials (like GaAs, InAs, GaP, InP,...) and III-nitride materials (GaN, InGaN, AlGaN,...). We review the way in which several innovative synthesis methods constitute the basis for the realization of highly controlled nanowires, and we combine this perspective with one of how the different families of nanowires can contribute to applications. One reason for the very intense research in this field is motivated by what they can offer to main-stream semiconductors, by which ultrahigh performing electronic (e.g., transistors) and photonic (e.g., photovoltaics, photodetectors or LEDs) technologies can be merged with silicon and CMOS. Other important aspects, also covered in the review, deals with synthesis methods that can lead to dramatic reduction of cost of fabrication and opportunities for up-scaling to mass production methods.

Synthesis and Applications of III-V Nanowires

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

Emerging Applications for High K Materials in VLSI Technology

https://iopscience.iop.org/article/10.1088/1361-6641/aad655/pdf

How to control defect formation in monolithic III/V hetero-epitaxy on (100) Si? A critical review on current approaches

Physical neural networks made of analog resistive switching processors are promising platforms for analog computing State-of-the-art resistive switches rely on either conductive filament formation or phase change These processes suffer from poor reproducibility or high energy consumption, respectively Herein, we demonstrate the behavior of an alternative synapse design that relies on a deterministic charge-controlled mechanism, modulated electrochemically in solid-state The device operates by shuffling the smallest cation, the proton, in a three-terminal configuration It has a channel of active material, WO3 A solid proton reservoir layer, PdHx, also serves as the gate terminal A proton conducting solid electrolyte separates the channel and the reservoir By protonation/deprotonation, we modulate the electronic conductivity of the channel over seven orders of magnitude, obtaining a continuum of resistance states Proton intercalation increases the electronic conductivity of WO3 by increasing both the carrier density and mobility This switching mechanism offers low energy dissipation, good reversibility, and high symmetry in programming

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Protonic solid-state electrochemical synapse for physical neural networks.

After 50 years of Moore’s Law, Si CMOS, the mainstream logic technology, is on a course of diminishing returns. The use of new semiconductor channel materials with improved transport properties over Si offer the potential for device scaling to nanometer dimensions and continued progress. Among new channel materials, III-V compound semiconductors are particularly promising. InGaAs is currently the most attractive candidate for future III-V based n-type MOSFETs while InGaSb is of great interest for p-channel MOSFETs. At the point of most likely deployment, devices based on these semiconductors will have a highly three-dimensional architecture. This paper reviews recent progress toward the development of nanoscale III-V MOSFETs based on InGaAs and InGaSb with emphasis on scalable technologies and device architectures and relevant physics. Progress in recent times has been brisk but much work remains to be done before III-V CMOS can become a reality.

Nanometer-Scale III-V MOSFETs

InGaAs has recently emerged as the most attractive non-Si n-channel material for future nano-scale CMOS. InGaAs n-channel MOSFETs promise to advance Moore's Law by allowing continued scaling through a reduction in footprint and operating voltage without compromising performance. This paper reviews recent advances in some of the key enabling process technology of InGaAs MOSFETs. It also outlines some of the challenges that need to be overcome before this new device family can become a reality.

InGaAs MOSFETs for CMOS: Recent advances in process technology

We propose and demonstrate a novel test structure to characterize the electrical properties of nano-scale metal-semiconductor contacts. The structure is in essence a two-port transmission line model (TLM) with contacts in the nanometer regime. Unlike the conventional TLM, two types of Kelvin measurements are possible. When performed on devices with different contact spacing, this allows the extraction of the contact resistance, the semiconductor sheet resistance, and the metal sheet resistance. For this, a 2-D distributed resistive network model has been developed. We demonstrate this technique in Mo/n+-InGaAs contacts with contact lengths from 19 to 450 nm where we have measured an average contact resistivity of 0.69±0.3 Ω·μm2. For relatively long contacts , this corresponds to an extremely small contact resistance of 6.6±1.6 Ω·μm.

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

This letter introduces a novel alcohol-based digital etch technique for III–V FinFET and nanowire MOSFET fabrication. The new technique addresses the limitations of the conventional water-based approach in enabling structures with sub-10-nm 3-D features. Using the same oxidation step, the new technique shows an etch rate of 1 nm/cycle, identical to the conventional approach. Sub-10 nm fins and nanowires with a high mechanical yield have been achieved. InGaAs nanowires with a diameter of 5 nm and an aspect ratio greater than 40 have been demonstrated. The new technique has also been successfully applied to InGaSb-based heterostructures, the first demonstration of digital etch in this material system. Vertical InGaAs nanowire gate-all-around MOSFETs with a subthreshold swing of 70 mV/decade at ${V} _{\mathrm { {DS}}}=$ 50 mV have been obtained at a nanowire diameter of 40 nm, demonstrating the good interfacial quality that the new technique provides.

Wenjie Lu

Papers

Protonic solid-state electrochemical synapse for physical neural networks.

Nanometer-Scale III-V MOSFETs

InGaAs MOSFETs for CMOS: Recent advances in process technology

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

Alcohol-Based Digital Etch for III–V Vertical Nanowires With Sub-10 nm Diameter