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Robert K. Montoye
Researcher at IBM
Publications - 117
Citations - 3658
Robert K. Montoye is an academic researcher from IBM. The author has contributed to research in topics: Register file & Dynamic logic (digital electronics). The author has an hindex of 27, co-authored 117 publications receiving 3472 citations. Previous affiliations of Robert K. Montoye include Twitter.
Papers
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Proceedings ArticleDOI
Stable SRAM cell design for the 32 nm node and beyond
Leland Chang,David M. Fried,John M. Hergenrother,Jeffrey W. Sleight,R.H. Dennard,Robert K. Montoye,Lidija Sekaric,Sharee J. McNab,Anna W. Topol,C.D. Adams,Kathryn W. Guarini,Wilfried Haensch +11 more
TL;DR: This work demonstrates the smallest 6T and full 8T-SRAM cells to date and provides a much greater enhancement in stability by eliminating cell disturbs during a read access, thus facilitating continued technology scaling.
Journal ArticleDOI
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
Leland Chang,Robert K. Montoye,Yutaka Nakamura,Kevin A. Batson,Richard J. Eickemeyer,Robert H. Dennard,Wilfried Haensch,Damir Jamsek +7 more
TL;DR: An eight-transistor (8T) cell can be designed without significant area penalty over 6T-SRAM while providing substantially improved variability tolerance and low-voltage operation with no need for secondary or dynamic power supplies.
Proceedings ArticleDOI
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
Jae-sun Seo,Bernard Brezzo,Yong Liu,Benjamin D. Parker,Steven K. Esser,Robert K. Montoye,Bipin Rajendran,Jose A. Tierno,Leland Chang,Dharmendra S. Modha,Daniel J. Friedman +10 more
TL;DR: A new architecture is proposed to overcome scalable learning algorithms for networks of spiking neurons in silicon by combining innovations in computation, memory, and communication to leverage robust digital neuron circuits and novel transposable SRAM arrays.
Proceedings ArticleDOI
A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm 2
TL;DR: In this paper, a switch-capacitor DC-DC voltage converter in 45nm SOI CMOS leverages on-chip trench capacitors to achieve 90% efficiency at an output of 2.3A/mm2 for 2V-to-0.95V conversion at 100MHz.
Patent
Multi-chip integrated circuit module
TL;DR: In this paper, a multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package, where low resistivity signal posts are provided within the lateral separation between adjacent die in the second set.