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Showing papers by "Wolfgang Fichtner published in 1991"


Journal ArticleDOI
TL;DR: In this paper, the impact of the cell pitch on the turn-off performance and the on-state voltage was studied for arrays with constant cathode area as well as for single-cell structures.
Abstract: 2.5-kV thyristor devices have been fabricated with integrated MOS controlled n/sup +/-emitter shorts and a bipolar turn-on gate using a p-channel DMOS technology. Square-cell geometries with pitch variations ranging from 15 to 30 mu m were implemented in one- and two-dimensional arrays with up to 20000 units. The impact of the cell pitch on the turn-off performance and the on-state voltage was studied for arrays with constant cathode area as well as for single-cell structures. By realizing MOS components with submicrometer channel lengths, scaled single cells are shown to turn off with current densities of several kiloamperes per square centimeter at a gate bias of 5 V. In the case of multi-cell ensembles, turn-off performance is limited due to inhomogeneous current distribution. Critical process parameters as well as the device behavior were optimized through multidimensional numerical simulation. >

37 citations


Journal ArticleDOI
TL;DR: An appropriate error indicator is developed based on a divergence free upwinding (finite element) discretization and it is indicated that it is sufficient only for a reverse-biased p-n junction to refine the grid according to the error in the Poisson equation.
Abstract: A method of computing the error in the solution of the semiconductor current continuity equations as well as the error in the terminal currents is proposed An appropriate error indicator is developed based on a divergence free upwinding (finite element) discretization The grid used for discretization is adapted to the error in the solution by dynamically adding or removing grid points in order to improve the solution and thus the terminal currents The examples indicate that it is sufficient only for a reverse-biased p-n junction to refine the grid according to the error in the Poisson equation In the forward biased case, it is necessary to take into account the error in the current continuity equation in order to guarantee exact terminal currents >

21 citations


Journal ArticleDOI
TL;DR: In this article, an array-type MCT was fabricated using a BiMOS process with additional power-specific fabrication steps, and the combination of anode current and blocking voltage values was the highest ever reported on MCT devices (2 kV, 5 A, in 2 mu s).
Abstract: Experimental results are reported for array-type MCT devices fabricated using a BiMOS process with additional power-specific fabrication steps. Stationary measurements of both the thyristor forward behavior and the intrinsic p-channel MOSFET switch characteristics are an indication of the device quality. Through dynamic testing procedures, the device was analyzed in its transient current handling. The combination of anode current and blocking voltage values is the highest ever reported on MCT devices (2 kV, 5 A, in 2 mu s). >

16 citations


Journal ArticleDOI
TL;DR: A new and efficient problem formulation with a complexity proportional to the circuit size is presented that allows the optimization of large circuits with reasonable effort and may be stopped prematurely while comparing different implementation alternatives.

12 citations


Proceedings ArticleDOI
08 Dec 1991
TL;DR: In this paper, the authors report on the effectiveness of these different approaches and their parasitic influence on the turn-on characteristic and the maximum turn-off current capability of large MCT-IGBT ensembles.
Abstract: The dynamic characteristics of large MCT (MOS controlled thyristor) ensembles have been improved by integrating IGBT (insulated-gated bipolar transistor) cells for turn-on and different schemes of cathode and anode shorting for turn-off Such MCT-IGBT ensembles with integrated shorts are able to turn off 4 A (240 A-cm/sup -2/) at 1000 V in typically 15 mu s in the inductive clamped mode The authors report on the effectiveness of these different approaches and their parasitic influence on the turn-on characteristic and the maximum turn-off current capability The implementation of permanent cathode shorts has lead to an increase of the maximum turn-off current of large MCT ensembles, whereas anode shorting leads to faster turn-off and lower tail currents A careful design of the IGBT turn-on cell and placement is required for proper MOS turn-on even at low anode voltages >

9 citations


Proceedings ArticleDOI
Wolfgang Fichtner1, J. Burgler1, H. Dettmer1, H. Lendenmann1, Stefan Müller1, M. Westermann1 
22 Apr 1991
TL;DR: The authors give an overview of the status of CAD tools in power IC design, especially the use of simulation tools and computer-aided layout techniques, and illustrate the possibilities of these tools with two examples from a recent MOS controlled thyristor (MCT) design effort.
Abstract: The authors give an overview of the status of CAD (computer-aided design) tools in power IC design, especially the use of simulation tools and computer-aided layout techniques. They illustrate the possibilities of these tools with two examples from a recent MOS controlled thyristor (MCT) design effort. >

5 citations


Proceedings ArticleDOI
25 Feb 1991
TL;DR: The authors present a method for extracting timing constraints from a behavioral description, architectural restrictions, component timing requirements and protocol specifications, combined in a timing constraint graph that can be solved in polynomial time using algorithms known from symbolic layout compaction.
Abstract: For controller synthesis to be successful, detailed knowledge of the timing constraints of the system under synthesis is essential. The authors present a method for extracting timing constraints from a behavioral description, architectural restrictions, component timing requirements and protocol specifications. The timing constraints are combined in a timing constraint graph that can be solved in polynomial time using algorithms known from symbolic layout compaction. >

2 citations