A novel multiple-time programmable (MTP) single-poly EEPROM cell based on a half-MOS device is presented. The proposed cell is fabricated in a standard complementary metal-oxide-semiconductor (CMOS) process without any additional mask or process step. It is based on a novel approach, which provides many advantages with respect to the state-of-the-art standard MTP cells, in terms of area, program/erase performance, and endurance. A test-chip is fabricated in a standard 0.13 μm CMOS process and extensive experimental results are provided.

Half-MOS Single-Poly EEPROM Cell in Standard CMOS Process

A new fully logic process compatible 2T multitime programmable (MTP) memory cell has been introduced for embedded logic nonvolatile memory (NVM) applications. The cell adopts a novel contact coupling gate structure as an additional control gate for highly efficient operation and high-density memory applications. A new 2T n-channel MTP 2-Kb memory test chip has been also successfully demonstrated on pure 0.18- CMOS logic process without extra masking or process step. Furthermore, the embedded 2T MTP cell performs an efficiently program/erase operation by CHE injection and FN tunnel with highly reliable endurance and retention characteristics.

A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process

A multitime programmable memory cell with improved MOS capacitor is proposed in this paper The improved MOS capacitor has p-type junction near the channel, which prevents the capacitor from deep depletion, and this helps to improve the cell’s program/erase efficiency and stability A test chip is fabricated using a 013- $\mu \text{m}$ standard CMOS process without any extra masks or process modification The experimental results show that the proposed cell achieves much faster and more stable program/erase speed than do the cells using the conventional MOS capacitor Furthermore, endurance characteristics of up to 10-k cycles and data retention at 250 °C are presented, and the results indicate that the improved MOS capacitor does not affect the cell’s reliability

Multitime Programmable Memory Cell With Improved MOS Capacitor in Standard CMOS Process

In this letter, we propose a new fully logic-process-compatible multitime programmable (MTP) memory cell for high-density logic nonvolatile memory (NVM) applications. A very small logic NVM MTP cell has been demonstrated on pure 0.18-μm CMOS process and logic design rules without extra masking and process steps. The MTP cell can be efficiently programmed and erased with a novel tiny contact coupling structure. Very small cell size, fast programming speed, and superior reliability characteristic make the new contact coupling gate MTP cell be one of the most promising solutions in advanced logic NVM application.

A High-Density MTP Cell With Contact Coupling Gates by Pure CMOS Logic Process

A single-poly electrically erasable programmable ROM (EEPROM) cell compatible with standard CMOS process is proposed. With respect to the classical embedded NOR cell, it can be programmed and erased by Fowler-Nordheim tunneling with single-bit granularity. The memory cell is based on a novel writing-inhibition scheme enabled by the combination of the body effect with multiple half-MOS devices. Experimental results on programming, erasing, inhibition, reading, and cycling endurance are provided using a 0.13 μm standard CMOS process.

Half-MOS Based Single-Poly EEPROM Cell With Program and Erase Bit Granularity

This letter presents a novel differential p-channel logic-compatible multiple-time programmable (MTP) memory cell. This MTP cell has a pair of floating gates, and performs differential read to increase the on/off window. Additionally, a novel self-recovery operation is implemented to boost the floating gate level, thus avoiding the charge-loss problem due to the thin gate oxide requirement in advance logic nonvolatile memory applications. This differential cell with its self-recovery operation is a very promising MTP solution for gate oxide layer with a 70 A thickness, and can be implemented by 3.3 V I/O in 90 nm and the advanced CMOS logic processes such as 45 nm and beyond.

A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation

This work presents a novel differential n-channel logic-compatible multiple-time programmable (MTP) memory cell. This cell features double sensing window by a differential pair of floating gates, and therefore increases the retention lifetime of the nonvolatile memory effectively. Also, a self-selective programming (SSP) method is innovated in writing one pair differential data by a single cell without increasing any design or process complexity in peripheral circuit. The differential cell is a promising MTP solution to challenge thin floating gate oxide below 70 A for 90 nm complementary metal–oxide–semiconductor (CMOS) node and beyond.

http://iopscience.iop.org/article/10.1143/JJAP.49.04DD13/pdf

Wun-Jie Lin

Papers

A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation

A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell