Three-dimensional (3D) additive manufacturing techniques have been utilized to make 3D electrical components, such as resistors, capacitors, and inductors, as well as circuits and passive wireless sensors. Using the fused deposition modeling technology and a multiple-nozzle system with a printing resolution of 30 μm, 3D structures with both supporting and sacrificial structures are constructed. After removing the sacrificial materials, suspensions with silver particles are injected subsequently solidified to form metallic elements/interconnects. The prototype results show good characteristics of fabricated 3D microelectronics components, including an inductor–capacitor-resonant tank circuitry with a resonance frequency at 0.53 GHz. A 3D “smart cap” with an embedded inductor–capacitor tank as the wireless passive sensor was demonstrated to monitor the quality of liquid food (e.g., milk and juice) wirelessly. The result shows a 4.3% resonance frequency shift from milk stored in the room temperature environment for 36 h. This work establishes an innovative approach to construct arbitrary 3D systems with embedded electrical structures as integrated circuitry for various applications, including the demonstrated passive wireless sensors. A three-dimensional (3D) printing technology makes possible arbitrary-shaped, integrated microelectronic components and circuitry with existing products such as food containers. Customizing microsystems through layer-by-layer manufacturing techniques is an attractive proposition. However, the polymers used typically offer poor conductivity, making them unsuitable for microelectronic device applications. Liwei Lin and colleagues from the USA and Hsinchu address this problem by printing resistor, capacitor, and inductor devices composed of hollow polymer tubes. By injecting silver paste into the tubes, curing the metal, and removing the polymer support, they are able to generate intricate yet functional 3D circuits. The team demonstrates the potential of their approach by creating a “smart cap”—a wireless inductive sensor incorporated into a milk carton lid. The sensor detects shifts in liquid dielectric constant signals to warn consumers about potential food safety issues.

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3D-printed microelectronics for integrated circuitry and passive wireless sensors

Impedance matching networks for nonlinear devices such as amplifiers and rectifiers are normally very challenging to design, particularly for broadband and multiband devices. A novel design concept for a broadband high-efficiency rectenna without using matching networks is presented in this paper for the first time. An off-center-fed dipole antenna with relatively high input impedance over a wide frequency band is proposed. The antenna impedance can be tuned to the desired value and directly provides a complex conjugate match to the impedance of a rectifier. The received RF power by the antenna can be delivered to the rectifier efficiently without using impedance matching networks; thus, the proposed rectenna is of a simple structure, low cost, and compact size. In addition, the rectenna can work well under different operating conditions and using different types of rectifying diodes. A rectenna has been designed and made based on this concept. The measured results show that the rectenna is of high power conversion efficiency (more than 60%) in two wide bands, which are 0.9–1.1 and 1.8–2.5 GHz, for mobile, Wi-Fi, and ISM bands. Moreover, by using different diodes, the rectenna can maintain its wide bandwidth and high efficiency over a wide range of input power levels (from 0 to 23 dBm) and load values (from 200 to 2000 Ω). It is, therefore, suitable for high-efficiency wireless power transfer or energy harvesting applications. The proposed rectenna is general and simple in structure without the need for a matching network hence is of great significance for many applications.

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Matching Network Elimination in Broadband Rectennas for High-Efficiency Wireless Power Transfer and Energy Harvesting

Radio frequency (RF) electrostatic discharge (ESD) protection design emerges as a new challenge to RF integrated circuits (IC) design, where the main problem is associated with the complex interactions between the ESD protection network and the core RFIC circuit being protected. This paper reviews recent development in RF ESD protection circuit design, including mis-triggering of RF ESD protection structures, ESD-induced parasitic effects on RFIC performance, RF ESD protection solutions, as well as characterization of RF ESD protection circuits.

A review on RF ESD protection design

This paper presents a novel approach to design RF tunable bandstop filters with constant absolute bandwidth. The filters are based on a doublet configuration which is attractive for high-order filter designs. In the doublet, two varactor-tuned resonators, arranged in a mirror-symmetrical manner, are coupled to a main transmission line. A novel coupling scheme is utilized between the resonators and the main line. Theoretical analysis indicates that, as the resonant frequency varies, the coupling coefficient within the fixed coupling region can be inherently changed to desirable values to meet the requirement of constant absolute bandwidth. Using the coupling scheme, constant absolute bandwidth can be obtained without extra circuits to control the coupling strengths. For demonstration, first-order and high-order filters are designed. Comparisons of experimental and simulated results are presented to verify the theoretical predications.

RF Tunable Bandstop Filters With Constant Bandwidth Based on a Doublet Configuration

A review of some of the available technologies for inductor hybrid integration is given in this paper. In accordance with low voltage and high current requirements, low-temperature co-fired ceramics (LTCC) technology is identified to be a suitable candidate for power electronics passives integration. This paper will discuss the various limitations of the current LTCC processing technique and introduce a fabrication technique which will open a new field for chip inductors for hybrid power electronics integration. The design of an LTCC inductor will also be presented. This inductor exhibits an inherent current dependent inductance, leading to high efficiency at low loads as an important systems advantage in portable electronics.

A Class of Ceramic-Based Chip Inductors for Hybrid Integration in Power Supplies

On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-/spl mu/m CMOS and BiCMOS processes, are presented.

A mixed-mode ESD protection circuit simulation-design methodology

This letter reports the design and fabrication of on-chip radio-frequency (RF) inductors with integrated-ferrite thin Alms, which show substantial improvement over air-cored inductors, e.g., 19%-38% and 17%-28% increase in inductance (L) for Y2.8B0.2Fe5O12 and Co7ZrO9 thin-film inductors, respectively, and 32%-55% improvement in quality factor (Q) of Co7ZrO9 sample, which are all measured across 0.1-9 GHz. It demonstrates the feasibility for making the ferrite-integrated high-performance compact on-chip inductors for RF ICs.

Ferrite-Integrated On-Chip Inductors for RF ICs

The trial-and-error approach still dominates on-chip electrostatic discharge (ESD) protection circuit design. We present a new predictive mixed-mode ESD protection simulation-design methodology, which involves multiple-level electro-thermal-process-device-circuit-layout coupling in an ESD protection simulation that solves complex electro-thermal equations self-consistently at process, device and circuit levels, in a coupled fashion. In this way, we can investigate ESD protection circuit behavior without any pre-assumption. Practical design examples in commercial 0.35 /spl mu/m CMOS are presented.

Mixed-mode ESD protection circuit simulation-design methodology

On-chip electrostatic discharge (ESD) protection design is a challenging IC design problem. New computer-aided design (CAD) tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel smart parametric-checking mechanism and a new intelligent CAD tool, entitled ESD inspector, developed for full-chip ESD-protection circuitry-design verification. Capability of the new tool is demonstrated using a practical design example in a 0.35-/spl mu/m BiCMOS technology.

Xiaokang Guan

Papers

A review on RF ESD protection design

A mixed-mode ESD protection circuit simulation-design methodology

Ferrite-Integrated On-Chip Inductors for RF ICs

Mixed-mode ESD protection circuit simulation-design methodology

ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism