This paper presents a mostly digital multiplying delay-locked loop (MDLL) architecture that leverages a new time-to-digital converter (TDC) and a correlated double-sampling technique to achieve subpicosecond jitter performance. The key benefit of the proposed structure is that it provides a highly digital technique to reduce deterministic jitter in the MDLL output with low sensitivity to mismatch and offset in the associated tuning circuits. The TDC structure, which is based on a gated ring oscillator (GRO), is expected to benefit other PLL/DLL applications as well due to the fact that it scrambles and first-order noise shapes its associated quantization noise. Measured results are presented of a custom MDLL prototype that multiplies a 50 MHz reference frequency to 1.6 GHz with 928 fs rms jitter performance. The prototype consists of two 0.13 μm integrated circuits, which have a combined active area of 0.06 mm 2 and a combined core power of 5.1 mW, in addition to an FPGA board, a discrete DAC, and a simple RC filter.

A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

A Review on Power Supply Induced Jitter

This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.

Efficient Jitter Analysis for a Chain of CMOS Inverters

An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.

Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

A novel phase-noise-filtering technique based on phase-domain averaging is proposed to suppress the large injection spurs and poor high-frequency phase noise of inductor-less injection-locked phase-locked loops (IL-PLLs). Demonstrated using a 1.2-GHz fractional-N IL-PLL based on a capacitive-ring-coupled ring oscillator, wideband spur-and-phase-noise suppression of up to 20 dB is achieved allowing for phase noise as low as −146 dBc/Hz at 30-MHz offset with a 2-MHz resolution. This allows for an inductor-less alternative to LC-based PLLs in scaled-digital CMOS technologies. The 65-nm CMOS prototype improves 10-MHz phase noise from −115 to −135 dBc/Hz, injection spurs from −40.5 to −57 dB, and integrated jitter from 3.57 to 1.48 ps while occupying an area of 0.6 mm2 and consuming 19.8 mW from a 0.85-V supply, resulting in an FoM and FoMJitter of −163 and −223.6 dB, respectively.

A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs

This paper demonstrates a very simple and highly accurate expression of power supply-induced jitter sensitivity transfer function for CMOS buffer chain. The transfer function is mainly a function of the maximum and minimum propagation delay of the buffer chain. The function can be easily obtained and used in jitter budget calculation.

Propagation Delay-Based Expression of Power Supply-Induced Jitter Sensitivity for CMOS Buffer Chain

A detailed study of reference frequency spurious spectrum components in edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this paper. The reference spur components caused by the delay mismatch between delay cells in the voltage controlled delay line (VCDL), as well as the spur components due to phase detector locking error are analyzed and unified. A digital calibration method is proposed to lower the spurious tone for the DLL based frequency multiplier output. An error detector compares the timing difference of each sub-period and compensates for the error by adjusting the delay time of each delay cell. The simulation results show a reduction of reference spur.

Spur analysis and reduction of edge combining DLL-based frequency multiplier

An improved technique is presented for a differential pair operating as a single-ended to differential converter. Common source stages are used to compensate the output amplitude difference, and a resistor in series with a dummy transistor is in parallel with only one common source stage to compensate the output phase difference. The simulation results show that for the output differential signal, HD2 < -48.5 dBc, HD3 < -50.5 dBc, the amplitude difference < 4.5% and the absolute phase difference < 3deg with 0.18 mum-CMOS technology, over the frequency range from 1.6 GHz to 2.4 GHz. The simulation results agree with the improved technique well.

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A Compensation Way for a Differential Pair to Achieve a High Performance Single-Ended to Differential Converter

A reduced reference spur multiplying delay-locked loop

Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.

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Xin Jie Wang

Papers

Propagation Delay-Based Expression of Power Supply-Induced Jitter Sensitivity for CMOS Buffer Chain

Spur analysis and reduction of edge combining DLL-based frequency multiplier

A Compensation Way for a Differential Pair to Achieve a High Performance Single-Ended to Differential Converter

A reduced reference spur multiplying delay-locked loop

A Static Phase Offset Reduction Technique for Multiplying Delay-Locked Loop