In this article, high-performance vertical gallium nitride (GaN)-on-GaN Schottky barrier diodes (SBDs) with helium (He)-implanted edge termination (ET) structure were demonstrated for the first time. Owing to the feature of He-implanted ET structure, the peak electric field crowding effect underneath the Schottky contact metal edge has been significantly reduced, thus increasing the breakdown voltage <inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {BR}}}$ </tex-math></inline-formula> of the diodes. Under the same testing conditions, <inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {BR}}}$ </tex-math></inline-formula> was increased from 862 to 1725 V for the devices with He-implanted ET structure, which also have low specific differential ON-resistance <inline-formula> <tex-math notation="LaTeX">${R}_{{\scriptscriptstyle {\mathrm {ON}}}}$ </tex-math></inline-formula> of 5.1 <inline-formula> <tex-math notation="LaTeX">$\text{m}\Omega \cdot {\mathrm {cm}}^{2}$ </tex-math></inline-formula> and low turn-on voltage <inline-formula> <tex-math notation="LaTeX">${V}_{{\scriptscriptstyle {\mathrm {ON}}}}$ </tex-math></inline-formula> of 0.63 V. Given <inline-formula> <tex-math notation="LaTeX">${V}_{{\scriptscriptstyle {\mathrm {ON}}}}$ </tex-math></inline-formula> of < 0.7 V, the vertical GaN SBDs with He-implanted ET structure show the highest <inline-formula> <tex-math notation="LaTeX">${V}_{{\mathrm {BR}}}$ </tex-math></inline-formula> in the reported work up to today.

1.7-kV Vertical GaN-on-GaN Schottky Barrier Diodes With Helium-Implanted Edge Termination

The invention provides an insulated gate bipolar transistor, and relates to the field of semiconductor devices. The insulated gate bipolar transistor comprises an N+ emitting electrode, a Pwell region, an N drift region, a carrier storage layer, a P injection layer and a region without circular cells, wherein the Pwell region is internally provided with a first groove gate and a second groove gate; the region without circular cells is internally provided with a local grid electrode narrowing bias structure, wherein the local grid electrode narrowing bias structure comprises a first grid electrode and a second grid electrode, a first transverse broadening structure is formed at the bottom of the first grid electrode, and the broadening direction faces the second grid electrode; a second transverse broadening structure is formed at the bottom of the second grid electrode, and the broadening structure faces the first grid electrode. The insulated gate bipolar transistor solves the technical problem that the withstand voltage of the insulated gate bipolar transistor is reduced caused after the technical concentration of the carrier storage layer of the insulated gate bipolar transistorin the prior art is increased, and original withstand voltage capacity can be maintained while the drop voltage is greatly reduced, so that the technical effect of comprehensively improving the parameter capacities of the device is reached.

Insulated gate bipolar transistor

<p indent="0mm">Silicon (Si) material is the mainstream semiconductor material for a long time because of its relatively excellent high-temperature resistance, radiation resistance, low price, and huge reserves. However, with the rapid development of power electronics technology, the development of technology has reached a bottleneck period, and Moore’s law has gradually failed. The existing silicon-based semiconductor devices are close to the theoretical limit of Si materials and can no longer meet the performance requirements of future power devices. However, the cost of transistors is constantly rising, and the performance improvement is slow, gradually moving towards the post-Moore era. To further improve the performance of the device, it is necessary to seek new technologies or new materials to support the continuous development of power devices, and the core of the progress of power semiconductor devices is the development of semiconductor materials. As the third generation of wide band gap semiconductors, gallium nitride (GaN) has been superior to Si in terms of material properties. GaN has the advantages of a wide band gap, high critical field strength, high electron saturation velocity, high conductivity, high-temperature resistance, and high voltage resistance. Compared with traditional Si-based power devices, it not only has higher breakdown voltage, low on-resistance, high electron mobility and good thermal conductivity, but also has smaller device volume and better heat dissipation performance under the same performance, which greatly reduces power consumption and achieves the effect of energy saving and emission reduction. The cost of early GaN single crystal preparation and epitaxial growth is beyond reach. However, with the mature development of growth technology, not only the cost of GaN single crystal substrate and its epitaxial growth is decreasing, but also the quality is gradually increasing, which lays a solid foundation for the wide application of GaN power devices in the future. This paper lists the main physical parameters of GaN and other semiconductor materials, the preparation of GaN single crystal, and the main methods of its epitaxy growth, and describes the advantages of GaN power devices in the current environment. For the device structure, the problems of the lateral device and the advantages of the vertical device are listed, and why the vertical device can become the mainstream structure of future power devices is explained. On this basis, the structure, working principle, research progress, and existing problems of vertical current aperture GaN transistor (CAVET), trench GaN MOSFET, vertical trench MOSFET based on <italic>in-situ</italic> oxidation GaN interlayer (GaN OG-FET), and vertical GaN fin field effect transistor (GaN FinFET) are introduced in detail. The performance parameters of vertical GaN power transistors mentioned in this paper are summarized in tables according to device types and time sequence, and the general direction of the development of GaN power transistors in the future is proposed. For integrated circuit systems, the special requirements and key technologies of GaN power devices in driver chips are summarized. Finally, for the current market environment, listing the vertical GaN power transistor in the medium and low voltage range is a more popular and promising application scenario. 

垂直氮化镓功率晶体管及其集成电路的发展状况

The threshold voltage (V
 TH) stability in GaN fat field-effect transistors (FATFETs) with a large channel area of ∼6.2 × 104
 μm2 was studied using drain current vs gate voltage (I
 D–V
 G) characteristics. Each measurement was found to positively shift the previous I
 D–V
 G curve, and V
 TH eventually saturated with increasing number of measurements. The saturated V
 TH was ∼0.8 V for measurements in which V
 G ranged from −10 to 25 V and was ∼8 V for measurements in which the V
 G ranged from −10 to 40 V. Moreover, the positive gate bias stress increased V
 TH to 12.3 V. These shifts of V
 TH can be explained by electron trapping; according to charge-pumping measurements, the traps cannot exist in the oxide or the oxide/p-GaN interface but can exist near the surface region in p-GaN layers in GaN FATFETs. Scanning transmission electron microscopy and electron energy-loss spectroscopy analyses revealed the presence of oxygen within several atomic layers of p-GaN from the oxide/p-GaN interface. This intermixed oxygen might be the origin of the n-type behavior of the p-GaN surface; furthermore, the oxygen is speculated to be related to the traps. Surprisingly, similar incorporated oxygen was observed even in the surface region of as-grown p-GaN layers.

https://iopscience.iop.org/article/10.1149/2162-8777/acd1b4/pdf

Gate-Bias-Induced Threshold Voltage Shifts in GaN FATFETs

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are researched. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes device total triggering path shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than DDSCR. For thermal performance, mostly heat builds up nearby lateral PNP transistor at first, then the peak point of heat turns to main SCR path along with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Compared with DDSCR, the conclusions are proposed. On the condition of TLP test simulation analyses, the triggering voltage is decreased 31%, the holding voltage is increased 16.8%, ESD design window is optimized 44.5% and on-resistance is lower. When TLP stress is 2.67A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two device enlarges further. According to VF-TLP test results, clamping ability of PNP_DDSCR under transient overshoot voltage is more stable in condition of fast turn-on speed. When the VF-TLP stress is 0.1A, the overshoot voltage of PNP_DDSCR device is the 37% of DDSCR. While PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

Novel Dual-Direction ESD Device with Lateral PNP Transistor

In this work, a vertical gallium nitride (GaN)-based trench MOSFET on 4-inch free-standing GaN substrate is presented with threshold voltage of 3.15 V, specific on-resistance of 1.93 mΩ·cm2, breakdown voltage of 1306 V, and figure of merit of 0.88 GW/cm2. High-quality and stable MOS interface is obtained through two-step process, including simple acid cleaning and a following (NH4)2S passivation. Based on the calibration with experiment, the simulation results of physical model are consistent well with the experiment data in transfer, output, and breakdown characteristic curves, which demonstrate the validity of the simulation data obtained by Silvaco technology computer aided design (Silvaco TCAD). The mechanisms of on-state and breakdown are thoroughly studied using Silvaco TCAD physical model. The device parameters, including n--GaN drift layer, p-GaN channel layer and gate dielectric layer, are systematically designed for optimization. This comprehensive analysis and optimization on the vertical GaN-based trench MOSFETs provide significant guide for vertical GaN-based high power applications. 

/pdf/1-3-kv-vertical-gan-based-trench-mosfets-on-4-inch-free-27mtxxql.pdf

1.3 kV Vertical GaN-Based Trench MOSFETs on 4-Inch Free Standing GaN Wafer

APartial Narrow Mesa (PNW)SJ IGBT structure is proposed in this paper.With a non-connected SJ implemented inthe PNW IGBT,the proposed structure combines the injection enhancement effectsfrom bothPNW and SJ structure,which improvesthecarrier concentrationnear the cathode sideand reducesthe on-state voltage drop.Meanwhile, the implementationof theSJ structure improvesthe blockingcapabilityat an equivalent device thickness and reduces the turn-off loss. Therefore,the proposed structure has a better Vce and Eofftrade-off. These advantages have beendemonstratedby 2-Dnumerical simulation.

A Partial Narrow Mesa Superjunction IGBT

Direct bidirectional current discharge paths between input/output (I/O) and ground (GND) are imperative to achieve robust charged device model (CDM) protection for very stringent design window in advanced low-voltage (LV) processes. In this brief, a compact and fast response dual-directional silicon-controlled rectifier (CFR-DDSCR) has been proposed. Using P-electrostatic discharge (ESD) implantation layer to implement each diode-triggered silicon-controlled rectifier (SCR) within only one n-well, the inherent defect of the prior art (i.e., the cumbersome p-well/n-well triggering diode) is eliminated, ensuring the low resistance of auxiliary triggering path and the compactness of silicon footprint. Moreover, by shielding all internal shallow trench isolation (STIs) with floating high- ${k}$ metal gates (HKMGs), an all-gate-bounded SCR structure is realized, and all triggering diodes evolve into gated diodes with compact current paths, thus improving the CDM protection capability greatly. Experimental results indicate that the CFR-DDSCR, with a design window suitable for 1.2 V-CMOS technologies, acquires a higher effective CDM robustness (73% improved), a faster turn-on speed (64% improved), and a more compact layout (31% shrunk) compared with its conventional counterpart, which is promising for the advanced LV CDM protection.

Compact and Fast Response Dual-Directional SCR for Nanoscale ESD Protection Engineering

Comparative study of the exponential-trap-based and the mobility-based space-charge-limited current models for organic diode modelling

In this paper, a novel all-high-K metal gate (HKMG)-bounded silicon-controlled rectifier (AHBSCR) is proposed for advanced electrostatic discharge (ESD) protection in FinFET processes. Depart from its prior arts, in AHBSCR, both the main SCR path and the triggering diode path are placed along the Fin direction, and all active areas are bounded by HKMG, thus expressing superior conduction capability under various ESD stresses and a more compact silicon footprint. Experimental results show that the proposed AHBSCR owns a suitable snapback window of 1.1 V–1.6 V, a fast turn-on speed of only 400 ps, an extreme low leakage current of less than 100 pA@-1 V as well as a figure of merit of 24.3 mA fF−1, indicating it is competent to replace the conventional FinFET diodes in rail-based ESD network to further improve the efficiency of ESD protection.

Xin Nan Lin

Papers

1.3 kV Vertical GaN-Based Trench MOSFETs on 4-Inch Free Standing GaN Wafer

A Partial Narrow Mesa Superjunction IGBT

Compact and Fast Response Dual-Directional SCR for Nanoscale ESD Protection Engineering

Comparative study of the exponential-trap-based and the mobility-based space-charge-limited current models for organic diode modelling

All-HKMG-bounded SCR for advanced ESD protection in 14 nm FinFET technology