A novel time-domain bulk-tuned offset cancellation technique is applied to a low-power high-precision dynamic comparator to reduce its input-referred offset with minimal additional power consumption and delay. The design has been fabricated in a commercially available 0.5-μm process. Measurement results of 10 circuits show a reduction of offset standard deviation from 5.415 mV to 50.57 μV, improved by a factor of 107.1. The offset cancellation scheme does not introduce observable offset or noise, and can achieve fast and robust convergence with a wide range of common mode input. Operating at a supply of 5 V and clock frequency of 200 kHz, the comparator together with the OC circuitry consumes 4.65 μW of power, or 23 pJ of energy per comparison.

A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation

Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a two-step incremental A/D converter (IADC) which extends the performance of an $N$ th-order IADC close to that of a $(2N-1)$ th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 V $_{\rm PP}$ and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm 2 , and it consumes only 10.7 µW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

This paper presents a multi-step incremental analog-to-digital converter (IADC) using multi-slope extended counting. Only one active integrator is used in the three-step conversion cycle. The accuracy of the IADC is extended by having it configured asmulti-slope ADCs in two additional steps. The proposed IADC uses the same circuitry as a first-order IADC (IADC1), but it exhibits better performance than a second-order IADC. For the same accuracy, the conversion cycle is shortened by a large factor (by more than 29 for the implemented device) compared with that of a conventional single-step IADC1. Fabricated in 0.18 $\mu \text{m}$ CMOS process, the prototype ADC occupies 0.5 mm2. With a 642 kHz clock, it achieves an SNDR of 52.2 dB in the first step. The SNDR is boosted to 79.8 dB in the second step and to 96.8 dB in the third step, over a 1 kHz signal band. The power consumption is 35 $\mu \text{W}$ from a 1.5 V power supply. This gives an excellent Schreier figure of merit of 174.6 dB.

A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting

In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

Incremental Delta-Sigma ADCs: A Tutorial Review

Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

A low-power and low-offset latched comparator using dynamic offset cancellation and a latch load is proposed. A latch load at the first stage provides the second stage with a large conversion gain and large trigger voltage. It reduces the power consumption and offset voltage of the comparator. The effectiveness of the proposed structure was verified by SPECTRE simulations.

Low-power and low-offset comparator using latch load

A new incremental ADC (IADC) is proposed which extends the order of a conventional incremental ADC from N to (2N − 1) by way of a two-step operation. For a given conversion time, the duration of each step can be optimised. For an Nth-order IADC, the performance is equivalent to that of a (2N − 1)-order converter. However, it only needs the same circuitry as the Nth-order one. The new IADC is hence more accurate, and also much more power-efficient than the conventional ones.

/pdf/two-step-incremental-analogue-to-digital-converter-4eqr1our09.pdf

Two-step incremental analogue-to-digital converter

Extended-counting A/D converters are proposed which achieve a high accuracy by performing the conversion in several cycles. During the first cycle, the circuit performs as an incremental ADC, while during the remaining ones it acts as a multi-slope counting converter. With only one opamp and a single-slope ADC, the accuracy is comparable to that of a second-order incremental ADC. A three-step A/D converter using only a single opamp and a two-slope ADC achieves an accuracy comparable to that of a third-order incremental ADC, but with much higher power efficiency.

/pdf/multi-step-extended-counting-analogue-to-digital-converters-1w2d6o01yv.pdf

Multi-step extended-counting analogue-to-digital converters

A novel ΔΣ analogue-to-digital (ADC) architecture is proposed for second-order noise shaping enhancement. The new architecture is less dependent on the opamp DC gain than the earlier ΔΣ ADC with second-order noise shaping enhancement. Also, the proposed architecture reduces the complexity of the clock generator and zero optimisation compared to the earlier one. A ΔΣ ADC using the new configuration was designed and simulated. The results verify the advantages of the proposed structure.

Y. Jung

Papers

Low-power and low-offset comparator using latch load

Two-step incremental analogue-to-digital converter

Multi-step extended-counting analogue-to-digital converters

Double noise coupling ΔΣ analogue-to-digital converter