This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Molybdenum disulfide holds great potential for advanced flexible electronic devices. Here, using a transferred gate technique, the authors fabricate molybdenum disulfide-based transistors with optimized device geometry and contact, improving device speed and demonstrating gigahertz circuits with voltage gain.

/pdf/few-layer-molybdenum-disulfide-transistors-and-circuits-for-19wjdet8ht.pdf

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

In this paper, an overview is given of the radar benefits of digital arrays in comparison with conventional phased arrays. Considered are passive and active phased arrays as well as subarray- and element-level digital arrays; their key differences are highlighted. A discussion of several radar attributes and performance measures follows to show the advantages and promise of element-level digital arrays as the newest generation architecture for radar and other electronic systems. Radar attributes considered are antenna patterns and beam control (including adaptive interference cancellation), dynamic range, in-band linearity, system phase noise, and angle measurement accuracy.

Benefits of Digital Phased Array Radars

In this paper, we propose a new class of operation of an RF oscillator that minimizes its phase noise. The main idea is to enforce a clipped voltage waveform around the LC tank by increasing the second-harmonic of fundamental oscillation voltage through an additional impedance peak, thus giving rise to a class-F 2 operation. As a result, the noise contribution of the tail current transistor on the total phase noise can be significantly decreased without sacrificing the oscillator's voltage and current efficiencies. Furthermore, its special impulse sensitivity function (ISF) reduces the phase sensitivity to thermal circuit noise. The prototype of the class-F 2 oscillator is implemented in standard TSMC 65 nm CMOS occupying 0.2 mm 2 . It draws 32–38 mA from 1.3 V supply. Its tuning range is 19% covering 7.2–8.8 GHz. It exhibits phase noise of -\hbox {139 dBc/Hz} at 3 MHz offset from 8.7 GHz carrier, translated to an average figure-of-merit of 191 dBc/Hz with less than 2 dB variation across the tuning range. The long term reliability is also investigated with estimated >10 year lifetime.

/pdf/an-ultra-low-phase-noise-class-f-2-cmos-oscillator-with-191-pvrkagjgjx.pdf

An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability

The development of two new types of high-density, electroless plated microelectrode arrays for CMOS-based high-sensitivity direct bacteria and HeLa cell counting are presented. For emerging high-sensitivity direct pathogen counting, two technical challenges must be addressed. One is the formation of a bacteria-sized microelectrode, and the other is the development of a high-sensitivity and high-speed amperometry circuit. The requirement for microelectrode formation is that the gold microelectrodes are required to be as small as the target cell. By improving a self-aligned electroless plating technique, the dimensions of the microelectrodes on a CMOS sensor chip in this work were successfully reduced to 1.2 $\mu {\rm m} \times \,$ 2.05 $\mu{\rm m}$ . This is 1/20th of the smallest size reported in the literature. Since a bacteria-sized microelectrode has a severe limitation on the current flow, the amperometry circuit has to have a high sensitivity and high speed with low noise. In this work, a current buffer was inserted to mitigate the potential fluctuation. Three test chips were fabricated using a 0.6- $\mu{\rm m}$ CMOS process: two with 1.2 $\mu {\rm m} \times\, $ 2.05 $\mu{\rm m}$ (1024 $\,\times\,$ 1024 and 4 $\,\times\,$ 4) sensor arrays and one with 6- $\mu{\rm m}$ square (16 $\,\times\,$ 16) sensor arrays; and the microelectrodes were formed on them using electroless plating. The uniformity among the 1024 $\,\times\,$ 1024 electrodes arranged with a pitch of 3.6 $\mu {\rm m} \times\, $ 4.45 $\mu{\rm m}$ was optically verified. For improving sensitivity, the trenches on each microelectrode were developed and verified optically and electrochemically for the first time. Higher sensitivity can be achieved by introducing a trench structure than by using a conventional microelectrode formed by contact photolithography. Cyclic voltammetry (CV) measurements obtained using the 1.2 $\mu {\rm m} \, \times \,$ 2.05 $\mu{\rm m}$ 4 $\,\times\,$ 4 and 6- $\mu{\rm m}$ square 16 $\,\times\,$ 16 sensor array with electroless-plated microelectrodes successfully demonstrated direct counting of the bacteria-sized microbeads and HeLa cells.

Development of Microelectrode Arrays Using Electroless Plating for CMOS-Based Direct Counting of Bacterial and HeLa Cells

The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance. The peak cut-off frequency (f T ) doubles from 209 GHz in the 90 nm node to 445 GHz at the 32 nm node. 1/f flicker noise reduces by an order of magnitude from the 0.13 um node to the 32 nm node. Transistor noise figure, high voltage tolerance, and quality factors of RF passives all show similar benefits from technology scaling.

https://www.intel.se/content/dam/doc/technology-brief/32nm-soc-with-rf-cmos-technology-paper.pdf

Y-L Lu

Papers

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications