This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Molybdenum disulfide holds great potential for advanced flexible electronic devices. Here, using a transferred gate technique, the authors fabricate molybdenum disulfide-based transistors with optimized device geometry and contact, improving device speed and demonstrating gigahertz circuits with voltage gain.

/pdf/few-layer-molybdenum-disulfide-transistors-and-circuits-for-19wjdet8ht.pdf

Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics

The vision of embedding connectivity into billions of everyday objects runs into the reality of existing communication technologies -- there is no existing wireless technology that can provide reliable and long-range communication at tens of microwatts of power as well as cost less than a dime While backscatter is low-power and low-cost, it is known to be limited to short ranges This paper overturns this conventional wisdom about backscatter and presents the first wide-area backscatter system Our design can successfully backscatter from any location between an RF source and receiver, separated by 475 m, while being compatible with commodity LoRa hardware Further, when our backscatter device is co-located with the RF source, the receiver can be as far as 28 km away We deploy our system in a 4,800 ft2 (446 m2) house spread across three floors, a 13,024 ft2 (1210 m2) office area covering 41 rooms, as well as a one-acre (4046 m2) vegetable farm and show that we can achieve reliable coverage, using only a single RF source and receiver We also build a contact lens prototype as well as a flexible epidermal patch device attached to the human skin We show that these devices can reliably backscatter data across a 3,328 ft2 (309 m2) room Finally, we present a design sketch of a LoRa backscatter IC that shows that it costs less than a dime at scale and consumes only 925 mW of power, which is more than 1000x lower power than LoRa radio chipsets

https://dl.acm.org/doi/pdf/10.1145/3130970

LoRa Backscatter: Enabling The Vision of Ubiquitous Connectivity

In this paper, an overview is given of the radar benefits of digital arrays in comparison with conventional phased arrays. Considered are passive and active phased arrays as well as subarray- and element-level digital arrays; their key differences are highlighted. A discussion of several radar attributes and performance measures follows to show the advantages and promise of element-level digital arrays as the newest generation architecture for radar and other electronic systems. Radar attributes considered are antenna patterns and beam control (including adaptive interference cancellation), dynamic range, in-band linearity, system phase noise, and angle measurement accuracy.

Benefits of Digital Phased Array Radars

A 2.4 GHz outphasing power amplifier (PA) is implemented in a 32 nm CMOS process. An inverter-based class-D PA topology is utilized to obtain low output impedance and good linearity in the outphasing system. MOS switch non-idealities, such as finite on-resistance and finite rise and fall times are analyzed for their impact on outphasing linearity and efficiency. Outphasing combining is performed via a transformer configured to achieve reduced loss at power backoff. The fabricated class-D outphasing PA delivers 25.3 dBm peak CW power with 35% total system Power Added Efficiency (includes all drivers). Average OFDM power is 19.6 dBm with efficiency 21.8% when transmitting WiFi signals with no linearization required. The PA is packaged in a flip-chip BGA package. Good linearity performance (ACPR and EVM) demonstrates the applicability of inverter-based class-D amplifiers for outphasing configurations.

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance. The peak cut-off frequency (f T ) doubles from 209 GHz in the 90 nm node to 445 GHz at the 32 nm node. 1/f flicker noise reduces by an order of magnitude from the 0.13 um node to the 32 nm node. Transistor noise figure, high voltage tolerance, and quality factors of RF passives all show similar benefits from technology scaling.

https://www.intel.se/content/dam/doc/technology-brief/32nm-soc-with-rf-cmos-technology-paper.pdf

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

This talk will present the stringent requirements of 4G systems, and the goals that reconfigurable circuits must achieve for a successful insertion in multi-band 4G front-ends. Despite of ever increasing number of bands, modes and radios, mobile phones need to be kept at reasonable form factor, cost, performance and power consumption. The RF front-end develops more and more to a bottleneck limiting cost, size and performance of future radios. This introduces challenging, but also very attractive insertion opportunities for tunable and reconfigurable devices based on GaAs/SOI/SOS/BST or MEMS technologies.

Requirements for reconfigurable 4G front-ends

A 12b 70MS/s sub-2 radix SAR ADC designed on Intel's 14nm tri-gate CMOS process is presented. It utilizes a startup calibration for correcting capacitor mismatches in its CDAC. The calibration is fully digital and doesn't require accurate references or input signals. The sub-2 radix architecture provides redundancy that improves speed. The comparator has a novel preamplifier that helps achieve low-noise and high-speed operation. The ADC achieves 68.1dB SNDR, 80dB SFDR, 70MS/s speed, and consumes 4.3mW power.

A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS

A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets. A high performance NMOS achieves an f T of 420GHz. Concurrently, a low leakage 30pA/um NMOS achieves an f T of 218GHz. Deep-nwell/guard rings improves noise isolation by >50dB. High Q inductors, >7V breakdown voltage power amplifier transistors, varactors, and precision passives are also presented.

A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

A 12-Gb/s transceiver in 32-nm bulk CMOS in described. Features include an 8.8–12.4-GHz LC-PLL with 0.4-ps jitter; a full-swing DLL and phase interpolator with LSB=2.6 ps and DNL≪1.2 ps; a 4.2-mW receiver front end with de-muxing comparator and precharge removal latch; and an all-digital duty cycle correction (DCC) loop. The transceiver receives and transmits PRBS23 data at 12 Gb/s with BER≪10−12 over a 6-in FR4 channel with 10 dB of loss, while consuming 37.8 mW (3.15 pJ/bit) from a 1-V supply, not including clock generation. A chip-to-chip link transmits and receives PRBS15 data at 11.6 Gb/s with BER≪10−12 over a 12-in. FR4 channel.

Jad B. Rizk

Papers

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

Requirements for reconfigurable 4G front-ends

A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS

A 32nm low power RF CMOS SOC technology featuring high-k/metal gate

A 12-Gb/s transceiver in 32-nm bulk CMOS