P
P. Vandervoorn
Researcher at Intel
Publications - 15
Citations - 1180
P. Vandervoorn is an academic researcher from Intel. The author has contributed to research in topics: Transistor & CMOS. The author has an hindex of 13, co-authored 15 publications receiving 1124 citations.
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Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Proceedings ArticleDOI
45nm High-k + metal gate strain-enhanced transistors
C. Auth,Annalisa Cappellani,J.-S. Chun,A. Dalis,Alison Davis,Tahir Ghani,G. Glass,Timothy E. Glassman,Michael K. Harper,Michael L. Hattendorf,P. Hentges,S. Jaloviar,Subhash M. Joshi,Jason Klaus,K. Kuhn,D. Lavric,M. Lu,H. Mariappan,Kaizad Mistry,B. Norris,Nadia M. Rahhal-Orabi,Pushkar Ranade,J. Sandford,Lucian Shifren,V. Souw,K. Tone,F. Tambwe,A. Thompson,D. Towner,T. Troeger,P. Vandervoorn,Charles H. Wallace,J. Wiedemer,Christopher J. Wiegand +33 more
TL;DR: In this article, two key process features that are used to make 45 nm generation metal gate + high-k gate dielectric CMOS transistors are highlighted in this paper.
Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Proceedings ArticleDOI
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
Chetan Prasad,Lei Jiang,Dhruv Singh,M. Agostinelli,C. Auth,P. Bai,Travis Eiles,J. Hicks,Chia-Hong Jan,Kaizad Mistry,Sanjay Natarajan,B. Niu,Paul A. Packan,Daniel Pantuso,Ian R. Post,S. Ramey,A. Schmitz,Sell Bernhard,S. Suthram,J. Thomas,Curtis Tsai,P. Vandervoorn +21 more
TL;DR: In this article, the authors describe various measurements on self-heat performed on Intel's 22nm process technology and outline its reliability implications, comparing them to thermal modeling results and analytical data.
Proceedings ArticleDOI
RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications
Chia-Hong Jan,M. Agostinelli,H. Deshpande,Mohammed A El-Tanani,Hafez Walid M,U. Jalan,L. Janbay,M. Kang,Hasnain Lakdawala,J. Lin,Y-L Lu,S. Mudanai,Joodong Park,Abdur Rahman,Jad B. Rizk,W.-K. Shin,Krishnamurthy Soumyanath,H. Tashiro,Curtis Tsai,P. Vandervoorn,J.-Y. Yeh,P. Bai +21 more
TL;DR: In this article, the authors examined the impact of silicon technology scaling trends and associated technological innovations on RF CMOS device characteristics, and the application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance.