This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained-Si hole mobility data are analyzed using six band k/spl middot/p calculations for stresses of technological importance: uniaxial longitudinal compressive and biaxial stress on [001] and [110] wafers. The calculations and experimental data show that low in-plane and large out-of-plane conductivity effective masses and a high density of states in the top band are all important for large hole mobility enhancement. This work suggests longitudinal compressive stress on [001] or [110] wafers and channel direction offers the most favorable band structure for holes. The maximum Si inversion-layer hole mobility enhancement is estimated to be /spl sim/ 4 times higher for uniaxial stress on (100) wafer and /spl sim/ 2 times higher for biaxial stress on (100) wafer and for uniaxial stress on a [110] wafer.

Uniaxial-process-induced strained-Si: extending the CMOS roadmap

In this paper, we explore the scaling limits of alternative gate dielectrics based on their direct-tunneling characteristics and gate-leakage requirements for future CMOS technology generations. Important material parameters such as the tunneling effective mass are extracted from the direct-tunneling characteristics of several promising high-/spl kappa/ gate dielectrics for the first time. We also introduce a figure-of-merit for comparing the relative advantages of various gate dielectrics based on the gate-leakage current. Using an accurate direct-tunneling gate-current model and specifications from the International Technology Roadmap for Semiconductors (ITRS), we provide guidelines for the selection of gate dielectrics to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies.

MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations

We report a new NBTI phenomenon for p-MOSFETs with ultra thin gate oxides. We demonstrate that in a CMOS inverter circuit, the interface traps generated under NBTI stressing in a p-MOSFET (corresponding to the "high" output state of the inverter) are subsequently passivated when the gate to drain voltage switches to positive (corresponding to the "low" output state of the inverter). As a result, it was found that this "Dynamic" NBTI (DNBTI) operating in a CMOS inverter circuit prolongs significantly the device lifetime while the conventional "static" NBTI (SNBTI) underestimates the device lifetime. Furthermore, the DNBTI effect is dependent on temperature and gate oxide thickness, but independent of operation frequency. A physical model is proposed for DNBTI that involves the interaction between hydrogen and silicon dangling bonds. This finding has significant impact on the determination of maximum operation voltage as well as lifetime projection for future scaling of CMOS devices.

Dynamic NBTI of PMOS transistors and its impact on device lifetime

Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 A and a leakage current of 5.02×10−5 A/cm2 at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (∼400 °C) used in the chemical-vapor deposition process.

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Effect of surface NH3 anneal on the physical and electrical properties of HfO2 films on Ge substrate

A physics-based 2-D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs (DG TFETs) with SiO2/HfO2 stacked gate-oxide structure has been developed in this paper. The parabolic-approximationtechnique, with suitable boundary conditions, has been used to solve Poisson’s equation in the channel region. Channel potential model is used to develop electric field expression. The drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the channel thickness. Threshold voltage has been extracted by maximum transconductance method. The proposed model also demonstrates that the proper choice of work function for both the latterly contacting gate electrode (near the source and drain) materials which can give better results in terms of input-output characteristics, SS, and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ than the conventional TFET devices. Although the proposed model has been primarily developed for Si-channel-based DM DG TFET devices, however, the model has also been shown to be applicable for other materials like SiGe (indirect bandgap) and InAs channel-based TFET structures. The results of the proposed model have been validated against the TCAD simulation results obtained by using SILVACO ATLAS device simulation software.

2-D Analytical Modeling of the Electrical Characteristics of Dual-Material Double-Gate TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure

We present a physical model to calculate the direct tunneling hole current through ultrathin gate oxides from the inversion layer of metal–oxide–semiconductor field-effect transistors. A parametric self-consistency method utilizing the triangular well approximation is used for the electrostatics of the inversion layer. For hole quantization in the inversion layer, an improved one-band effective mass approximation, which is a good approximation to the rigorous six-band effective mass theory, is used to account for the band-mixing effect. The tunneling probability is calculated by a modified Wentzel–Kramers–Brilliouin (WKB) approximation, which takes the reflections near the Si/SiO2 interfaces into account. It is found that the parabolic dispersion in the SiO2 band gap used in the WKB approximation is only applicable for hole tunneling in oxides thinner than about 2 nm and for low gate voltage. A more reasonable Freeman–Dahlke hole dispersion form with significantly improved fitting to all experimental data...

Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices

We present a systematic study of tunneling leakage current in metal gate MOSFETs and how it is affected by the work function of the metal gate electrodes. Physical models used for simulations were corroborated by experimental results from SiO/sub 2/ and HfO/sub 2/ gate dielectrics with TaN electrodes. In bulk CMOS results show that, at the same capacitance equivalent oxide thickness (CET) at inversion, replacing a poly-Si gate by metal reduces the gate leakage appreciably by one to two orders of magnitude due to the elimination of polysilicon gate depletion. It is also found that the work function /spl Phi//sub B/ of a metal gate affects tunneling characteristics in MOSFETs. It is particularly significant when the transistor is biased at accumulation. Specifically, the increase of /spl Phi//sub B/ reduces the gate-to-channel tunneling in off-biased n-FET and the use of a metal gate with midgap /spl Phi//sub B/ results in a significant reduction of gate to source/drain extension (SDE) tunneling in both n- and p-FETs. Compared to bulk FET, double gate (DG) FET has much lower off-state leakage due to the smaller gate to SDE tunneling. This reduction in off-state leakage can be as much as three orders of magnitude when high-/spl kappa/ gate dielectric is used. Finally, the benefits of employing metal gate DG structure in future CMOS scaling are discussed.

Metal gate work function engineering on gate leakage of MOSFETs

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.

Modeling of tunneling currents through HfO 2 and (HfO 2 ) x (Al 2 O 3 )/sub 1-x/ gate stacks

In this letter, we demonstrate for the first time that the Fermi-level pinning caused by the formation of Ta(N)-Si bonds at the TaN/SiO/sub 2/ interface is responsible for the thermal instability of the effective work function of TaN in TaN/SiO/sub 2/ devices after high temperature rapid thermal annealing (RTA). Because of weak charge transfer between Hf and Ta(N) and hence negligible pinning effect at the TaN/HfO/sub 2/ interface, the effective work function of TaN is significantly more thermally stable on HfO/sub 2/ than on SiO/sub 2/ dielectric during RTA. This finding provides a guideline for the work function tuning and the integration of metal gate with high-/spl kappa/ dielectric for advanced CMOS devices.

Fermi-level pinning induced thermal instability in the effective work function of TaN in TaN/SiO/sub 2/ gate stack

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 /spl Aring/ oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 /spl mu/m technology node, this structure could be scaled to EOT=12 /spl Aring/ if the maximum allowed gate leakage current is 1 A/cm/sup 2/ and EOT=9 /spl Aring/ if the maximum allowed gate leakage current is 100 A/cm/sup 2/.

Y.T. Hou

Papers

Direct tunneling hole currents through ultrathin gate oxides in metal-oxide-semiconductor devices

Metal gate work function engineering on gate leakage of MOSFETs

Modeling of tunneling currents through HfO 2 and (HfO 2 ) x (Al 2 O 3 )/sub 1-x/ gate stacks

Fermi-level pinning induced thermal instability in the effective work function of TaN in TaN/SiO/sub 2/ gate stack

Investigation of hole-tunneling current through ultrathin oxynitride/oxide stack gate dielectrics in p-MOSFETs