For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance. In the continuing drive to improve and miniaturize transistors, the microelectronics industry has recently adopted three-dimensional electronic gate structures. Another way of improving transistors is to use semiconductor materials with higher electron mobility than silicon, although this presents significant fabrication challenges. Katsuhiro Tomioka et al. combine the two approaches; they grow, with high precision, vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate. The resulting devices demonstrate superior transistor performance with excellent on/off switching behaviour and fast operation. Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

A III–V nanowire channel on silicon for high-performance vertical transistors

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

The reduction and removal of surface oxides from GaAs substrates by atomic layer deposition (ALD) of Al2O3 and HfO2 are studied using in situ monochromatic x-ray photoelectron spectroscopy. Using the combination of in situ deposition and analysis techniques, the interfacial “self-cleaning” is shown to be oxidation state dependent as well as metal organic precursor dependent. Thermodynamics, charge balance, and oxygen coordination drive the removal of certain species of surface oxides while allowing others to remain. These factors suggest proper selection of surface treatments and ALD precursors can result in selective interfacial bonding arrangements.

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GaAs interfacial self-cleaning by atomic layer deposition

Methods to extract trap densities at high-permittivity (k) dielectric/III-V semiconductor interfaces and their distribution in the semiconductor band gap are compared. The conductance method, the Berglund intergral, the Castagne–Vapaille (high-low frequency), and Terman methods are applied to admittance measurements from metal oxide semiconductor capacitors (MOSCAPs) with high-k/In0.53Ga0.47As interfaces with different interface trap densities. The results are discussed in the context of the specifics of the In0.53Ga0.47As band structure. The influence of different conduction band approximations for determining the ideal capacitance-voltage (CV) characteristics and those of the MOSCAP parameters on the extracted interface trap density are investigated. The origins of discrepancies in the interface trap densities determined from the different methods are discussed. Commonly observed features in the CV characteristics of high-k/In0.53Ga0.47As interfaces are interpreted and guidelines are developed to obtain...

/pdf/comparison-of-methods-to-quantify-interface-trap-densities-4qf6j9irvl.pdf

Comparison of methods to quantify interface trap densities at dielectric/III-V semiconductor interfaces

High-performance inversion-type enhancement-mode n-channel In053Ga047As MOSFETs with atomic-layer-deposited (ALD) Al2O3 as gate dielectric are demonstrated The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general A 05-mum gate-length MOSFET with an Al2O3 gate oxide thickness of 8 nm shows a gate leakage current less than 10-4 A/cm2 at 3-V gate bias, a threshold voltage of 025 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V The midgap interface trap density of regrown Al2O3 on In053Ga047As is ~14 x 1012/cm2 ldr eV which is determined by low-and high-frequency capacitance-voltage method The peak effective mobility is ~1100 cm2 / V ldr s from dc measurement, ~2200 cm2/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 05-10-MV/cm effective electric field

http://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=1238&context=nanopub

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric

Atomic layer deposition (ALD) provides a unique opportunity to integrate high-quality gate dielectrics on III-V compound semiconductors. The physics and chemistry of a III-V compound semiconductor surface or interface are problems so complex that even after three decades research understanding is still limited. We report a simplified surface preparation process using ammonium hydroxide (NH4OH) to remove the native oxide and make the hydroxylated GaAs surface ready for ALD Al2O3 surface chemistry. The effectiveness of GaAs passivation with ALD is demonstrated with small hysteresis, 1%-2% frequency dispersion per decade at accumulation capacitance, and a mid-bandgap D it of 8 times1011 to 1times 1012 cm-2 ldr eV-1determined by the Terman method. The results from ammonium sulfide [(NH4)2S-,and hydrofluoric acid (HF)-, and hydrochloric acid (HCl)-treated surfaces and a surface with native oxide are also presented to compare with the results from the ammonium-hydroxide-treated surface. Fermi-level unpinning is also easily demonstrated on the ALD HfO2 and p-type GaAs interface.

Simplified Surface Preparation for GaAs Passivation Using Atomic Layer-Deposited High- $\kappa$ Dielectrics

High-performance inversion-type enhancement-mode n-channel In053Ga047As MOSFETs with atomic layer deposited (ALD) Al2O3, HfO2, and HfAlO as gate dielectrics are demonstrated The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on III-V in general A 05-mum gate-length MOSFET with an Al2O3 gate oxide thickness of 8 nm shows a maximum drain current of 430 mA/mm and a transconductance of 160 mA/mm at drain voltage of 2 V The transconductance is improved to 180 mA/mm by implementing HfO2 or HfAlO as gate dielectrics with the same oxide thickness The peak effective mobility is -1200 cm2/Vs from dc measurement, ~ 4000 cm2/Vs after interface trap correction for HfO2/In053Ga047As NMOSFETs

https://engineering.purdue.edu/~yep/Papers/IEDM_2007_S23P08.pdf

High performance submicron inversion-type enhancement-mode InGaAs MOSFETs with ALD Al 2 O 3 , HfO 2 and HfAlO as gate dielectrics

High-performance inversion-type enhancement-mode n-channel MOSFETs on In-rich In0.75Ga0.25As using ALD Al2O3 as high-k gate dielectrics are demonstrated. The maximum drain current, peak transconductance, and the effective electron velocity of 1.0 A/mm, 0.43 S/mm and 1.0times107 cm/s at drain voltage of 2.0 V are achieved at 0.75-mum gate length devices. The device performance of In-rich InGaAs NMOSFETs with different indium contents, In0.53Ga0.47As, In0.65Ga0.35As and In0.75Ga0.25As, are systematically studied.

High-performance surface channel In-rich In 0.75 Ga 0.25 As MOSFETs with ALD high-k as gate dielectric

The electron mobility in Al2O3/InxGa1-xAs (x = 0.53, 0.65, or 0.75) metal-oxide-semiconductor field-effect transistors was analyzed for scattering by oxide charge, as well as interface charge and roughness, and compared with measured transfer characteristics from depletion to inversion. The analysis showed that, under strong inversion, the electron mobility was mainly limited by interface roughness. The extracted interface roughness from the measured data was two to seven times that of the interface between a high-k dielectric and Si, assuming the correlation lengths were comparable. Therefore, to fully benefit from the high bulk mobility of InGaAs, its interface roughness with the gate oxide needs to be further improved.

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Y. Xuan

Papers

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric

Simplified Surface Preparation for GaAs Passivation Using Atomic Layer-Deposited High- $\kappa$ Dielectrics

High performance submicron inversion-type enhancement-mode InGaAs MOSFETs with ALD Al 2 O 3 , HfO 2 and HfAlO as gate dielectrics

High-performance surface channel In-rich In 0.75 Ga 0.25 As MOSFETs with ALD high-k as gate dielectric

Analysis of Electron Mobility in Inversion-Mode $ \hbox{Al}_{2}\hbox{O}_{3}/\hbox{In}_{x}\hbox{Ga}_{1 - x}\hbox{As}$ MOSFETs