A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the proposed FTL continuously tunes the oscillator’s free-running frequency to ensure robust operation across PVT variations. The FTL resolves the race condition existing in injection-locked PLLs by decoupling frequency tuning from the injection path, such that the phase-locking condition is only determined by the injection path. This paper also introduces an accurate theoretical large-signal analysis for phase domain response (PDR) of injection-locked oscillators (ILOs). The proposed PDR analysis captures the asymmetric nature of ILO’s lock-in range, and the impact of frequency error on injection strength and phase noise performance. The proposed architecture and analysis are demonstrated by a prototype fabricated in 65 nm CMOS process with active area of $0.25\;\text{mm}^2$ . The prototype ILCM generates output clock in the range of 6.75–8.25 GHz by multiplying the reference clock by 64. It achieves superior integrated jitter performance of $190\;\text{fs}_{\text{rms}}$ , while consuming 2.25 mW power. This translates to an excellent figure-of-merit (FoM) of $-251\;\text{dB}$ , which is the best reported high-frequency clock multiplier.

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers

Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-locked clock multipliers have demonstrated some of the lowest jitters for a given power consumption (jitter-power ${\text {FoM}}_{j}$ metric). However, they contain a tradeoff between the spur and noise performance, where techniques incorporated for spur reduction adversely affect jitter or power performance. A new dividerless Type-I sampling PLL, called the reference sampling PLL (RS-PLL), which estimates the voltage-controlled oscillator (VCO) phase error by sampling the reference sine wave with a VCO square wave is demonstrated. A clock-and-isolation buffer which accelerates the VCO sine wave to a square wave sampling clock and simultaneously isolates the VCO tank from spur mechanisms in the sampler is included in place of a traditional reference buffer. By combining sampling clock buffer and VCO isolation functionalities into a single block, the RS-PLL eliminates the noise penalty of two separate buffers. The power penalty due to sampling at VCO frequency is restricted by limiting the activity of the switching circuits to the region around the reference zero crossing where the phase error information exists. The prototype RS-PLL implemented in 65-nm CMOS achieves a jitter-power ${\text {FoM}}_{j}$ of <−251 dB between 2.05 and 2.55 GHz with a reference spur of <−66 dBc at 50 MHz. In doing so, it improves upon the simultaneous noise and spur performance achieved by current state-of-the-art clock multipliers.

A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5–13 Gbps, implemented in 28 nm CMOS technology. The transmitter consists of 20:2 mux followed by a half-rate source-series terminated (SST) driver embedded with a 4 tap FFE and an analog equalizer. The receiver has an adaptive CTLE, 5 tap DFE, and fully digital CDR followed by 2:20 demux. At 13 Gbps, the transceiver can equalize 35 dB Nyquist loss at BER of 10-12. At 1.0 V supply, the transceiver consumes 49 mW/lane at 13 Gbps rate with full equalization capability. An LC VCO-based fractional PLL provides the clocking to quad TX/RX lanes using a low-power inductively tuned clock routing channel. The transceiver architecture not only enables the baud rate operation from 8.5 to 13 Gbps but also supports a wide range of oversampled subrates. This work represents the lowest reported power in its class to date, and the transceiver is suitable for many applications due to its comprehensive flexibility and power efficiency.

A 3.8 mW/Gbps Quad-Channel 8.5–13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS

A cognitive tri-band transmitter (TX) with a forwarded clock using multiband signaling and high-order digital signal modulations is presented for serial link applications. The TX features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at the receiver side, and then adapting modulation scheme, data bandwidth, and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from nonreturn to zero/Quadrature phase shift keying (QPSK) to Pulse-amplitude modulation (PAM) 16/256-Quadrature amplitude modulation(QAM). The proposed highly reconfigurable TX is capable of dealing with low-cost serial channels, such as low-cost connectors, cables, or multidrop buses with deep and narrow notches in the frequency domain (e.g., a 40-dB loss at notches). The adaptive multiband scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth. The implemented TX prototype consumes a 14.7-mW power and occupies 0.016 mm2 in a 28-nm CMOS. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy efficient figure of merit of 20.4 $\mu \text{W}$ /Gb/s/dB, which is calculated based on power consumption of transmitting per gigabits per second data and simultaneously overcoming per decibel worst case channel loss within the Nyquist frequency.

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection

This paper describes a 32.75-Gb/s voltage-mode transmitter (TX) with three-tap feed forward equalization that is fabricated in a 16-nm FinFET CMOS technology. The TX uses a dual regulator architecture to allow independent control of output swing, output common-mode, and equalization. A hybrid impedance control scheme is presented where the total number of driver slices is used for coarse impedance control, and analog loop-based voltage control is used for fine impedance control of the TX. A finite-impulse response compensation circuit to compensate for the data dependent current due to equalization is also presented. The TX consumes 120.8 mW with 0.9- and 1.2-V supplies, provides 0.25–0.9 Vpp output swing, and achieves total jitter of 6.49 ps–pp and random jitter of 220 fs–rms at 32.75 Gb/s with bit error rate of 1e-12.

A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS

This paper presents a quad-lane serial link that supports virtually all data center system-side and line-side communications standards from 85–13 Gbps, implemented in 28 nm CMOS The Tx is series source terminated with a 4-tap FFE Its swing ranges from 33 mV to 1 Vppd The Rx has CTLE, 5-tap DFE and CDR with 2x-oversampling, and baud-rate timing recovery options At 13 Gbps, the link can equalize 35 dB loss at Nyquist frequency with BER of 10−12 The link consumes 49 mW per lane at 13 Gbps This is the lowest reported power in its class to date, and with comprehensive programmability for a wide range of standards

A 3.8 mW/Gbps quad-channel 8.5–13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS

An 8.0 GHz to 12.2 GHz PLL with a capacitor multiplier-based active loop filter is designed in a 28 nm digital CMOS process. A passive loop filter-based version of the PLL is also implemented for comparison. While the PLL area is comparable to that of digital PLLs, the PLL performance is as good as that of an analog PLL that employs a passive loop filter. The capacitor multiplier-based active loop filter PLL has a jitter performance of 198 fs (rms), while its passive loop filter-based counterpart shows a jitter performance of 195 fs (rms). The PLL occupies 0.093 mm2 and consumes 15.5 mA at 1.0V.

A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

A SerDes operating from 8.5 to 11.4 Gb/s using nearly all CMOS digital circuits is presented. The transmitter achieves up to 1 Vdpp output swing with a DDJ as low as 2.7 ps. The receiver achieves an input sensitivity of less than 17 mVdpp. The chip is capable of transmitting and receiving data on an FR4 channel with 21 dB loss at Nyquist at a BER <; 10-12. The power consumption per Tx/Rx pair is 28.5 mW, and the active area is 0.047 mm2 in 28 nm CMOS. The chip reports the minimum SerDes area in the published literature.

Yang Liu

Papers

A 3.8 mW/Gbps Quad-Channel 8.5–13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS

A 3.8 mW/Gbps quad-channel 8.5–13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS

A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

A 2.8 mW/Gb/s quad-channel 8.5–11.4 Gb/s quasi-digital transceiver in 28 nm CMOS