Mohammed Abdul-Latif

TL;DR: It is confirmed, analytically and experimentally, that the phase noise of an M-stage CCRO improves by 10 M over that of a single ring oscillator and that thephase noise improvement bandwidth is a function of the coupling strength.

TL;DR: Channel reflection and cross-talk are excessive at 100Gb/s, which puts a ceiling on attainable BER, and considering practical equalization capabilities of a long-reach system (>30dB), 10dB package loss significantly limits the available channel reach.

TL;DR: Low power consumption and performance are achieved by combination of advanced 28 nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based VCO for four transceivers.

TL;DR: This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5-13 Gbps, implemented in 28 nm CMOS technology and represents the lowest reported power in its class to date.

TL;DR: The proposed architecture provides additional spur suppression of 30 dB compared to a conventional PLL and, to the best of the authors' knowledge, this PLL provides the best normalized reference-spur rejection in literature.