Yang Zheng

TL;DR: The simulation platform in this paper is calibrated using measured results from a fabricated nonvolatile processor and used to explore the design space for a nonVolatile processor with different architectures, different input power sources, and policies for maximizing forward progress.

TL;DR: This article explores the design space for an NVP across different architectures, input power sources, and policies for maximizing forward progress in a framework calibrated using measured results from a fabricated NVP and proposes a heterogeneous microarchitecture solution that more efficiently capitalizes on ephemeral power surpluses.

TL;DR: An array-level model to estimate the read/write energy and characterize the vertical access transistor is developed and a multi-directional write driver is proposed to mitigate the writer circuitry overhead, and a remote sensing scheme to take full advantage of limited on-die sensing resources is proposed.

TL;DR: This article summarizes mechanisms of both soft and hard errors of ReRAM cells and proposes a unified model to characterize different failure behaviors, which can extend the lifetime of Re RAM up to 75% over a design without hard error detection and up to 12% over the design with a “write-verify” detection mechanism.

TL;DR: Compared to previous 6T FinFET SRAMs, the proposed cells reduce the static leakage current, and enhance the write and read speed, and this structure is scalable for multi-ports.