This article presents a broadband power amplifier (PA) with a distributed-balun output network that provides the PA optimum load impedance over a wide bandwidth. The proposed output network comprises two coupled-line sections and absorbs the device output capacitance. It employs a scalable coupled-line modeling approach that captures both the magnetic (inductive) and electric (capacitive) couplings between windings with fewer parameters and supports a rapid design process. Closed-form design solutions, design space limitations, bandwidth limits, and design tradeoffs are derived and analyzed comprehensively. Its extension to differential output and common-mode response is also discussed in detail. As a proof of concept, a prototype PA is implemented for multiband fifth-generation (5G) applications in 45-nm SOI CMOS. With no biasing retuning or network reconfiguration, the PA consistently achieves >19.1 dBm $P_{\mathrm {sat}}$ , >37.3% peak power-added efficiency (PAE), 17.8–19.6 dBm $P_{\mathrm {1dB}}$ , and 36.6%–44.3% PAE $_{P\mathrm {1dB}}$ over 24–40 GHz, verifying the truly wideband large-signal matching. The PA demonstrates 5G new radio (NR) frequency range 2 (FR2) modulation signals over 24–42 GHz, covering n257/n258/n260 5G bands. For 5G NR FR2 800-MHz 2-CC 64-QAM signals (11.78-dB PAPR), the PA achieves 11.3-dBm/16.6% average $P_{\mathrm {out}}$ /PAE with −25.1-dB rms EVM at 28-GHz and 10.2-dBm/13.6% average $P_{\mathrm {out}}$ /PAE with −25.1-dB rms EVM at 37 GHz.

A Broadband Linear Ultra-Compact mm-Wave Power Amplifier With Distributed-Balun Output Network: Analysis and Design

This article presents a dual-band millimeter-wave front end in 45-nm CMOS silicon-on-insulator (SOI) for 5G applications. The front end is composed of a low-noise amplifier (LNA), power amplifier (PA), and a single-pole double-throw (SPDT) switch. A double-tuned PA is used and is based on a two-stage stacked amplifier with a reconfigurable load using SOI switches, so as to achieve an optimal load for both 28- and 39-GHz 5G NR bands. A wideband series-shunt switch is also developed with high power handling (P1dB >22 dBm) and $P_{\mathrm {sat}}$ is > 18.8 dBm and the peak PAE is 18% at 24–30 GHz and includes the switch loss and compression. For high-band operation, the gain at 36–40 GHz is 13.6 ± 1.5 dB with $P_{\mathrm {sat}} > 18$ dBm. To the best of our knowledge, this is the first front end that covers both the 24–28- and 37–40-GHz 5G bands with high output power and low-NF. Application areas are in multistandard base stations and small cells.

A High-Power 24–40-GHz Transmit–Receive Front End for Phased Arrays in 45-nm CMOS SOI

Millimeter wave (mmWave) bands attract large research interest as they can potentially lead to data rate of almost 10Gbits/sec and huge available bandwidth where as the microwave frequencies are limited to 1Gbits/s. This paper presents a comprehensive review of millimeter wave communications, frequency bands proposed by ITU, applications of mmWaves, advantages, limitations, challenges and research directions. Various antennas proposed by researchers for mmWave applications are described in detail. The described models are analyzed and compared with common antenna parameters. Applications like HD gaming, ultra high definition multimedia, security and surveillance demand for high data rates and more bandwidth. These all applications will drive mmWvaes technology to develop and offer wide bandwidths with high speed data.

https://iopscience.iop.org/article/10.1088/1742-6596/1804/1/012205/pdf

A Comprehensive Review on Millimeter Waves Applications and Antennas

This article analyses and demonstrates a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoM $_{T}$ of −191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm2 core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoMRMS of −239 dB. Its frequency acquisition time improves from 780 to 45 $\mu \text{s}$ with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels’ frequencies of IEEE-802.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to −35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).

Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication

Due to growing demand for higher data rates in wireless communication, high resolution requirement in radars, and emerging sensing applications, mm-wave frequency bands have become very attractive in recent years. Architectures and circuits of mm-wave transceivers are described and comparison of process technologies for mm-wave IC design is presented. Critical mm-wave circuit blocks and example implementations such as 60 GHz phased array, 28 GHz front-end, 79 GHz PMCW radar and 145 GHz FMCW radar are discussed and future trends are identified.

Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper)

This article presents a series voltage-combining Doherty power amplifier (PA) achieving high output power ( $P_{\mathrm {out}}$ ) and high power-back-off (PBO) efficiency for 28-GHz fifth-generation (5G) applications. We introduce a new transformer-based series output combiner design method to achieve a true-Doherty load modulation that uses a compact footprint. The output stages of the main PA and the auxiliary PA (aux. PA) both use a differential three-stacked FET topology for high output power without posing a reliability issue. The intermediate-node matching is achieved by using a shunt inductor for voltage waveform alignment and efficiency improvement. A modified differential quadrature hybrid is proposed to achieve the desired quadrature power splitting function without the need for an input balun. For the proof of concept, the proposed PA is implemented in a 22-nm CMOS fully depleted silicon-on-insulator (FD-SOI) technology with a core area of 0.2 mm2. At 28 GHz, the measured saturated output power ( $P_{\mathrm {sat}}$ ), 1-dB output compression point (OP1dB), and peak power-added efficiency (PAE) are 22.5 dBm, 21.1 dBm, and 28.5%, respectively. State-of-the-art International Technology Roadmap for Semiconductors (ITRS) figure-of-merit (FOM) and power density are achieved. The measured PAE at 6-dB PBO is 22.1%, which results in an efficiency enhancement ratio of 1.56/3.12 with respect to an ideal class-B and class-A PA. The proposed PA can support 2.4-Gb/s 64-quadratic amplitude modulation (64-QAM) and 0.8-Gb/s 256-QAM signal with a competitive average PAE. Excellent device reliability is validated by operating the implemented PA under 3-dB gain compression point for 12 h with less than 0.06-dB $P_{\mathrm {out}}$ variation. The proposed Doherty PA with a compact footprint is suitable for the integration purpose of future 5G multiple-input multiple-output (MIMO) and phased-array applications.

A 28-GHz SOI-CMOS Doherty Power Amplifier With a Compact Transformer-Based Output Combiner

This paper presents a Doherty power amplifier (PA) in 22nm FD-SOI for achieving high output power and high backoff efficiency for 28GHz 5G communications. The output stage of the main PA and the auxiliary PA both use a stacked-FET topology for high output power without posing a reliability issue. A dedicated transformer-based output matching network is proposed to achieve a true Doherty load modulation while maintaining a compact layout. The PA is fabricated in a 22nm FD-SOI technology with a core area of 0.2mm2. At 28GHz, the measured saturated output power (P sat ), 1dB output compression point (P 1dB ), and peak power-added efficiency (PAE) are 22.5dBm, 21.1dBm, and 28.5%, respectively. State-of-the-art ITRS figure-of-merit (FOM) and power density are achieved. The measured 6dB power back-off (PBO) PAE is 22.1%, which results in a PBO enhancement ratio of 1.56/3.12 with respect to a class-B/class-A PA. The proposed PA can support 2.4Gb/s 64-QAM and 0.8Gb/s 256-QAM signal with a competitive average PAE.

A 28GHz Voltage-Combined Doherty Power Amplifier with a Compact Transformer-based Output Combiner in 22nm FD-SOI

This article presents practical design considerations and methodologies for a 28-GHz front-end module (FEM) in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS technology for the fifth generation (5G) wireless communication. The design adopts a gain-boosting technique that is comprehensively analyzed with a transformer-based stacked-FET power amplifier (PA). Then, the co-design of the transmit/receive (T/R) switch with the PA and low-noise amplifier (LNA) is investigated, and an electrostatic-discharge (ESD)-aware T/R switch incorporating PA circuitry is proposed to leverage the Tx- and Rx-mode performance. Moreover, the robustness of standalone PA and Tx-mode FEM is simulated and experimentally verified. Furthermore, the ground return paths and supply parasitic paths of the adopted single-ended LNA together with the proposed T/R switch are studied, properly simulated, and assessed. Finally, the proposed PA topology is first verified standalone, exhibiting 32-dB power gain ( $G_{p}$ ), an 18.2-dBm output 1-dB compression point (OP1 dB), and a 31.1% power-added efficiency (PAE) at OP1 dB (PAE1 dB). Using this PA in the FEM yields a Tx-mode OP1 dB/PAE1 dB of 16 dBm/19.4%, and an average output power (Poutavg)/PAE of 10.1 dBm/8.3% for a 100-MHz bandwidth 256-QAM single-carrier signal at an error-vector magnitude (EVM) of −30 dB. In the Rx mode, noise figure (NF) and input-referred third-order intercept point (IIP3) are 3.2 and −5.4 dBm, respectively. A 2-kV human-body model (HBM) ESD protection of the FEM is predicted in transient simulations and measured with transmission line pulse (TLP) tests.

Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology

This paper presents a 23GHz low-phase-noise transformer-feedback differential VCO with a 27% frequency tuning range. By adding a source-bridging capacitor between the sources of the transistors that are connected to the two feedback transformers, the phase noise at $1/ f^{3}$ region is improved due to the suppression of flicker noise up-conversion. The proposed VCO is implemented in a 22nm FD-SOI technology with a low supply voltage of 0.65V. The measured phase noise is −106 dBc/Hz at lMHz frequency offset with power consumption of 11. 5mW, and the corresponding FOM and FOM T are 182.6 dBc/Hz and 191 dBc/Hz, respectively.

Yao Liu

Papers

A 28-GHz SOI-CMOS Doherty Power Amplifier With a Compact Transformer-Based Output Combiner

A 28GHz Voltage-Combined Doherty Power Amplifier with a Compact Transformer-based Output Combiner in 22nm FD-SOI

Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper)

Design and Analysis of a 28 GHz T/R Front-End Module in 22-nm FD-SOI CMOS Technology

A 23 GHz Low-Phase-Noise Transformer-Feedback VCO in 22nm FD-SOI with a FOMT of 191dBc/Hz